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UCC27712: Limiting Vboot

Part Number: UCC27712

Hello

Currently we are using the UCC27712 with a 12V power-supply and a highside mosfet with a 5V Vgs threshold-voltage.

We are driving the gate with the doubled voltage, which would actually be needed. We only need 5V Vgs, but the mosfet is driven with 12V Vgs, because the Cboot ist charged up on 12V.

Our mesurements show, that charging the gate far over the threshold-voltage causes some problematic switching-delays.

A great solution to this would be, not to charge Cboot up to 12V, instead limiting this volatge. Therefore we built in a z-diode between Rboot and Cboot and generated a voltage-drop form VDD to HB. This simply limits the voltage Vboot, which then drives the gate. Another solution would be, to build in a z-diode directly between the gate and the source of the mosfet. But this second solution is not prefered, because it increases the capacitance at the gate.

However, our prefered solution only works until we limit Vboot to 8V (Vz of the z-diode => 4.7V). When we increase the voltage-drop from VDD to HB further, the gate-driver stops driving the mosfet.

If I understood the datasheet correctly, then the uvlo of the UCC27712 is not the reason to this.

Why does this gate-driver stops switching, if Vboot ist limited this way? Would you recommend not to use the z-diode this way? Or is it unproblematic to generate a drop from VDD to HB?

With best regards

Eric Walser

  • Hello Eric,

    Thank you for the interest in the UCC27712. Since the UCC27712 is a 600V half bridge driver the VDD and HB UVLO thresholds are set expecting to drive 600-650V MOSFETs or IGBT's. Most high voltage MOSFETs have the parameters specified with 10V Vgs, so the driver bias voltage in many applications is expected to be 10V to 15V range, depending on if MOSFET or IGBT switching devices.

    The HB bias voltage can be reduced as you mention by having a voltage drop in the boot diode charging path. The HB UVLO turn on threshold is 8.2V typical and 9.2V maximum, so if the HB voltage is reduced below the HB UVLO the high side driver will not switch.

    One option would be to operate VDD at 10V which will reduce the Vgs to the high side MOSFET and low side MOSFET. I assume there is the same considerations on the low side MOSFET.

    If you want to reduce the Vgs below 9 to 10V there would need to be a voltage drop method from the driver to the MOSFET. You could have a Zener diode from the driver output to the MOSFET gate to reduce the Vgs. This may result in some negative Vgs voltage which should be OK with most MOSFETs which usually have a +/- Vgs rating.

    Confirm if this addresses your questions, or you can post additional questions on this thread.

    Regards,

  • Hello Richard

    Your answer addresses all of our questions.

    It helped a lot, thank you.

    Regards

    Eric