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UCC28251: Minimum on time and EN control discussion

Part Number: UCC28251

Hi team,

My customer whas two questions about this device,

1.Do we have some solution to use external circuit to limit UCC28251 minimum on time? They want to limit the minimu on time to 500ns. 

2. When customer want to turn off this IC in OCP event, they pull down EN and SS pin, SS pin connect BC817 to GND. But they can still detect PWM signal. Do you think what is the root cause?

Yellow: SS pink: PWM Output

Thanks.

BR,

CL

  • Hi Charles, I will reply to you tomorrow. —— Teng

  • Hi Teng,

    Do you have any updates about this question?

    Thanks.

    BR,

    CL

  • Hi Charles,

    Sorry I don't have such circuit that can limit the minimum on-time less than 500 ns.

    It is very strange why PWM still has output when SS pin is pulled to ground.  Can you test that will the controller shout down when pulling SS pin to ground externally during normal operation.

    Regards,

    Teng

  • Hi Feng,

    This waveform is tested during normal operation. And I saw there is another thread below may have the same issue. Could you please help explain more? Thanks.

    BR,

    CL

  • Hi Feng,

    Could you please help share some of your comments here? This is urgent case for my customer. Thanks.

    BR,

    CL

  • Hi Feng,

    I do not see any response to this problem. Would appreciate it if you can share your comments by April 20th. Thanks.

    BR,

    CL

  • Hi Charles,

    Sorry for the delay, since I just received the EVM.

    See the attached oscilloscope picture I tested by shorting SS to ground directly on the EVM, it shows pulling SS to ground can disable device and terminate PWM immediately.  Could you advice customer try to shorting SS ground directly and share me the schematic at teng-feng@ti.com

    Besides, the device can also be disabled by controlling EN pin. 

  • Hi Teng,

    Thank you for your response here. Customer cannot share schematic to us, for this is confidential information for them. They still have two questions about this device,

    1. Do you pull  EN pin to GND when you pull down the SS signal in the waveform you shared here?

    2.  Why output is not in the max duty in the SS stage? For COMP voltage is higher than RAMP here.

    CH1 COMP; CH2 RAMP; CH3 OUTPUT;

    BR,

    CL

  • Hi Charles,

    1./ I only pulled the SS pin to ground in the testing. Could customer try to short SS pin to ground directly? and they can only share a part of schematic. 

    2./ we can find there is an internal voltage offset at RAMP/CS pin from the block diagram.

    Regards,

    Teng

  • Hi Teng,

    Thank you for your response here.

    1.See SS control circuit from customer. Customer redo the test again, and they found that when pull down SS pin ,the output will be zero after 58ms. Do you have some explanation about this waveform?

    2. What is the internal voltage offset value? I cannot find it in our datasheet.

    Thanks.

    BR,

    CL

  • Hi Charles,

    1./ The shunt down circuit seems good. 

     Is it a secondary-side control or primary -side control?  Is it voltage mode control or peak current mode control?  I'd  like to see the circuit related to COMP, FB/EA-, REF/EA+, SS and RAMP/CS pin.  It is better to share the entire circuit related UCC28251 at my email teng-feng@ti.com  if it is unavailable here.

    Could you also provide the waveform of output voltage and comp pin on this picture?

    2./  It is 420 mV, the primary outputs begin to switch when COMP pin voltage is above the 420 mV internal offset. 

    Regards,

    Teng

  • Hi Teng,

    Thank you for your response here. Customer used secondary-side control and voltage control. Please see the latest waveform,

    When SS is short to GND,the PWM signal terminated after comp voltage equal to zero. But there is still have 2ms time delay. Is it related to the secondary-side control here? What kind of control mode you used when you short SS to GND? Thanks.

    Yellow=SS, Blue= COMP, Purple= PWM

    BR,

    CL

  • Hi Charles,

    Since there is no power stage, the FB/EA- pin voltage is equal to the REF/EA+ pin voltage due to virtual short circuit of error amplifier. 

    The compensation components net of error amplifier is an integration circuit, when pulling SS pin to ground, the output of error amplifier increases to zero slowly.

    Regards,

    Teng