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Part Number: TPS40303
I need to generate a 0.9V from a 12V input (17A max) and the design is highly constraint in efficiency.
I did look at the recommended TI parts for Altera/Intel but I need an efficiency above 90%. Which I achieved with a TPS40303 part in WeBench, selecting efficiency as the main criteria.
At start-up, the overshoot is around 0.950V where the input is between 0.87V and 0.93V. And there is a similar issue with the load transient response.
Is there anything I could do to lessen the overshoot ?
Pascale CrouzillatAt start-up, the overshoot is around 0.950V where the input is between 0.87V and 0.93V.
I meant : The FPGA specifies its power input between 0.87V an 0.93V
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Are you referring to simulation results in WEBENCH? I see it going all the way to 0.98V in simulation. It should be possible to minimize the overshoot by increasing the output capacitance and also tuning the compensation.
In reply to Pascale Crouzillat:
Do you have schematic and wave forms you can share? For the startup, you may be able to extend the soft start time by adding a larger value capacitor on the EN/SS pin to reduce the overshoot at start up For the load transient, add output capacitors and/or changing the frequency compensation to increase the bandwidth as Gerold is suggesting.
BSR-MV 10A to 25A Applications
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