UCC28056: output can not be maintained at desired voltage

user3899198

Part Number: UCC28056

Hello，E2E TI Expert ;

I am now using your CRM PFC controller UCC28056, and I am now with some problems with the controller;

1) The DC output voltage rises with the increase of the input AC power voltage, and it is difficult to maintain the desired set value of 400VDC; My test data are as follows:

Vinac_RMS(V)	Iinac_RMS(A)	Vout(VDC)	Rload(Ω)	Pout(W)	η
85	0.677	211	820	54.3	94.4%
90	0.696	220	820	59.0	94.2%
100	0.63	222	820	60.1	95.4%
110	0.669	239	820	69.7	94.7%
120	0.696	254	820	78.7	94.2%
150	0.667	277	820	93.6	93.5%
180	0.701	310	820	117.2	92.9%
200	0.681	322	820	126.4	92.8%
210	0.687	332	820	134.4	93.2%
220	0.688	340	820	141.0	93.1%
230	0.676	344	820	144.3	92.8%
240	0.686	349	820	148.5	90.2%
Note：Desired Vout voltage :400VDC.

2) It seems that in all working states, the circuit is always in CRM working mode, even though the load is small, the circuit is still not in DCM working state.

（08-04）UCC28056 Application Question.docx

over 4 years ago

0 user3899198 over 4 years ago

Prodigy 105 points

（08-05）VOSNS abnormal waveform.docx

0 Benjamin Lough over 4 years ago in reply to user3899198

TI__Mastermind 26645 points

Hi,

I would suggest making the following changes based on your power stage:

Change R24 to 3kOhm

Change C17 to 10pF

Change C14 to 22nF

Increase R23 to ~800kOhm

Make R16 a valid resistance for programming the valley delay. Either 18kOhm or 27kOhm should be fine.

Also I would suggest taking a look at the layout for the VOSNS divider. This divider should follow the output voltage of the PFC. From the waveform, it looks like there are sudden abrupt changes in the VOSNS amplitude. You might be getting coupling into the VOSNS divider that is corrupting the output voltage feedback.

Best Regards,

Ben Lough

0 user3899198 over 4 years ago in reply to Benjamin Lough

Prodigy 105 points

（0805）Reply to parameter change.docx

0 Benjamin Lough over 4 years ago in reply to user3899198

TI__Mastermind 26645 points

Hi,

Could you share the following waveforms?

COMP, VOSNS, Vout, ZCD/CS

Also please take a look at ZCD/CS compared to the divided down drain waveform. Please refer to figure 28, 29 and 30 in the UCC28056 datasheet.

Best Regards,

Ben Lough

0 user3899198 over 4 years ago in reply to Benjamin Lough

Prodigy 105 points

Hi Ben,

I tested the waveform of the VOSNS and ZCD/CS pin, seems quite different from the UCC28056 Datasheet（0806）VOSNS Pin & ZCD-CS Pin waveform.docx

0 Benjamin Lough over 4 years ago in reply to user3899198

TI__Mastermind 26645 points

Hi user3899198,

There is an offset in the ZCD/CS pin waveform. Judging by the shape of the inductor current and ZCD/CS waveform at 85Vac and 100Vac, you are seeing cycle by cycle current limit as well due to the distortion on the ZCD/CS pin. The ZCD/CS pin should follow the voltage across the current sense resistance when the MOSFET is on and follow the MOSFET drain waveform when the MOSFET is off.

I would suggest taking a look at different points in the ZCD/CS divider to identify the distortion source. It should look like a smooth, linearly rising ramp when the FET is on and 0V when the FET is off. Next look at the voltage on C11/C12. This voltage should follow the MOSFET drain voltage when the MOSFET is off and should follow the voltage on the current sense when the MOSFET is on.

Also I would suggest probing the ZCD/CS pin with "tip and barrel" to minimize the probability of noise coupling into the signal from the probe gnd clip.

Best Regards,

Ben Lough

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UCC28056: output can not be maintained at desired voltage