Hi,
datasheet 8.2, functional block diagram seems weird:
Nothing can pull CT down to GND.
Do you wanted to mean something with CT pin comes from the drain of the left side N-ch MOSFET; whilst the source of that MOSFET is at GND?
What happens if I tie the other pin of the timer capacitor to VDD instead of GND? Will the startup reset time be short, but a response to MR=L is a long pulse?
Thanks,
Tamas