we are realising a 3...4 kW bridgeless PFC with AC switches (common source FETs).
The line voltage range is 198 ... 305Vac and the dc bus voltage should be low as possible.
If the peak voltage of the line voltage gets higher than 85% of the dc bus voltage the current shape is not stable.
Also at light loads we get problems, there are low frequency steps in the current.
Therefore it is very importent for us to get all information of the current synthesizer.
In the UCC28070EVM the used value of the Rsynth is about 235% than of the formula in the datasheet.
I can understand the formula, but I can not check the scaling, because it depends of the internal structure of the IC.
The voltage at Rsynth is the difference between Vsense and Vinac.
I think, the principle operation is like this:
GDx high: Two internal capacitors are coupled to the inputs CSx via two impedance converters.
GDx low: The source current of Rsynth discharges the two internal capacitors via some current mirrors.
The voltage of the capacitors are the outputs of the current synthesizer.
Please check the scaling in the formula and give us all possible information to understand the limits of the current synthesizer.