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UCC28070: Current Synthesizer - calculation of Rsynth - different results between datasheet and EVM board

Part Number: UCC28070


we are realising a 3...4 kW bridgeless PFC with AC switches (common source FETs).
The line voltage range is 198 ... 305Vac and the dc bus voltage should be low as possible.
If the peak voltage of the line voltage gets higher than 85% of the dc bus voltage the current shape is not stable.
Also at light loads we get problems, there are low frequency steps in the current.

Therefore it is very importent for us to get all information of the current synthesizer.
In the UCC28070EVM the used value of the Rsynth is about 235% than of the formula in the datasheet. 

I can understand the formula, but I can not check the scaling, because it depends of the internal structure of the IC.

The voltage at Rsynth is the difference between Vsense and Vinac.
I think, the principle operation is like this:
GDx high: Two internal capacitors are coupled to the inputs CSx via two impedance converters.
GDx low: The source current of Rsynth discharges the two internal capacitors via some current mirrors.
The voltage of the capacitors are the outputs of the current synthesizer.

Please check the scaling in the formula and give us all possible information to understand the limits of the current synthesizer.

Best regards
Christian Strebe

  • Hello Christian,


    Thank you for your interest in the UCC28070 PFC controller.


    Your interpretation of the internal working of the current synthesizer is correct.
    Capacitors are charged up, then ramped down based on mirrored current through Rsynth.


    Without divulging internal design “secrets” I can assure you that the synthesizer is quite linear and the internal down-slope is accurately emulated when the Rsynth value calculated by the equation is used.

    Thinking graphically, the voltge at the CSx input starts at a level and goes up. At the end other PWM on-time, the synthesizer starts ramping down from that peak and ends up where the CSx voltage started.


    Rsynth values deviating from the formula can be used to advantage is certain cases where non-linearities come into play. A higher resistance results in a slower down-slope, so internal Vcs ends higher than it started each cycle. The current amplifier averages this higher and the PWM on-times are higher than needed. The voltage amplifier output must reduce to compensate to keep Vout regulated.

    However, the overall half-cycle current waveshape is exaggerated with convex sides and a flattened top, which could compensate for distortions from other sources.


    Conversely, an undersized Rsynth value provides a faster down-slope so Vcs ends up lower than where is started. The CA average is lower so PWM on-time is too little. VAO boosts the error to keep regulation so all cycles are expanded which tends to produce concave sides to the half-cycle with a peaky top.  This can counteract other distortions.  

    Adjusting Rsynth higher or lower may allow you to fine tune the iTHD for a certain set of operating conditions. Of course THD at other conditions will also change, so it is a tradeoff of accepting higher THD here to reduce THD there, where “there” is more important than “here”.
    I believe the large deviation for Rsynth in the UCC28070EVM is to accommodate the variable inductance from the “swinging-choke” design, instead of a fixed inductance.


    The steps in the current waveform at light load have nothing to do with the synthesizer.  The synthesizer only acts on the information presented at the CSx input.
    These steps are the result of trapped magnetizing current in the current-sense transformers (CT) during discontinuous conduction at light load. DCM current has resonant ringing current at the end of each cycle.

    This ringing current flows through the CT and the instantaneous value of this current adds to the next cycles’ starting current in the CT. If the resonant current was positive when the next cycle starts, it subtracts from the sensed current to Rs, lowering the starting voltage. If the resonant current was negative when the next cycle starts, it adds to the sensed current to Rs, raising the starting voltage.

    As the AC line rises and falls along the sine wave, the resonant CT magnetizing current changes up and down depending on the timing intervals within each switching cycle. The net result is that the current sense introduces steps along the sine wave. The width of the steps depends on the resonant frequency when in DCM. Once CCM is established, this phenomenon goes away.


    Making the CT inductance as high as possible minimizes the resonant peaks and frequency and mitigates the problem. In addition, Section on page 35 of the datasheet discussed a technique to adjust the CSx signals with an offset and/or ramp to help reduce the distortion. Some manual trial-and-error adjustments of values may be needed to optimize the effects.