Hi,
Could you please confirm VDD range in datasheet explanation?
P1 shows
• Ensured RESET/RESET for VDD = 0.7 V to 6 V
Which information is correct for VDD range? I guess P1 information is incorrect..
Regards,
Nagata.
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Hi,
Could you please confirm VDD range in datasheet explanation?
P1 shows
• Ensured RESET/RESET for VDD = 0.7 V to 6 V
Which information is correct for VDD range? I guess P1 information is incorrect..
Regards,
Nagata.
Hi Nagata-san,
During power-up, there is also a (tSTRT) time that is not shown in the waveform. The tSTRT time is the time that the IC is "waking up". Therefore, the total time when the /RESET pin goes high during power up is tSTRT + tD. Depending on different conditions like VDD and temp, tSTRT should be less than 300uS. Please see below.
Ben