TPS54325: Could you tell me about the TPS54325's detecting UVLO?

Hi,

Toggle EN can restart the chip if converter is latched by trip UVP.

Thank you very much for the answer, Andy Chen-san.
Please let me teach in addition.

Currently, when my customer drops VIN instantaneously (12 V ⇒ 4 V)
The output stops and latch phenomenon occurs.

Probably, I think that output is lowered and UVP is applied.

Therefore, when VIN is lowered like the above phenomenon,
can you show distribution (3 sigma) of VIN voltages at UVP's detected?
※ If you aren't doing such a special test,
　I'll trying to challenge whether you can convince customers with the UVP detection voltage distribution (3 sigma).
※Since I know that it'll fit within of 65 to 75% at the electric characteristic range,
　my customer said me showed a distribution of 3 sigma !

Please help me！！

Best regards,
Masumi Sekiguchi

Hi

Do you have ctm application circuit? what's the output voltage? did ctm test Vout waveform while doing input drop?

Thank you for contacting me.

＞Do you have ctm application circuit?
No, I don't.

＞what's the output voltage?
Output voltage is 5V.

＞did ctm test Vout waveform while doing input drop?
I don’t know if customer saw the vout waveform unless I ask the customer.

So…
If necessary we will ask you whether you can obtain the customer's circuit diagram and the waveform at the time of measurement,
How is it?

If you receive it, expectation for data presentation that are required may increase, but if it is important so I'll get it.

Best regards,
Masumi Sekiguchi

Ok, inform me your email add and ctm's email add, let's check it directly with ctm to fix it early.

Hi Masumi,

Why would customer have their input voltage drop fast from 12V to 4V and would like to have a stable output? Could they let input voltage drop below UVLO and then rise input voltage again to wake up the device?

What I could find for the UVth is the ATE measured min, typ and max value: 69.542%, 69.586%, 69.673%

Best,
Anthony

Everyone (Anthony-san, Andy-san),
Thank you for contacting me.


To Andy-san.

＞Ok, inform me your email add and ctm's email add,
let's check it directly with ctm to fix it early.

⇒Sorry, it's confirmed once more.
　Should I get the customer's circuit diagram and the waveform?


To Anthony-san.

＞Why would customer have their input voltage drop fast from 12V to 4V and would like to have a stable output?

⇒My customer don’t have to get stable output voltage,
　he hate that the IC stops and doesn't return from latching.
　(I think from the situation I talked about at a meeting with customer.)

＞Could they let input voltage drop below UVLO and then rise input voltage again to wake up the device?

⇒Because of the evaluation condition assuming after mass production,
　Adjusting the input voltage is difficult and it is necessary to respond to this condition.

＞What I could find for the UVth is the ATE measured min, typ and max value: 69.542%, 69.586%, 69.673%

⇒How many pieces of data did you confirm?
　Is it available as 3 sigma distribution data?

Thank you very much for enthusiastic support.
Please continue to help, I would appreciate your help.

Masumi Sekiguchi

Hi Masumi,

I think the data I showed you is based on 30pcs sample test. I could not find 3 sigma data for it. 

Best,

Anthony

Thank you very much for contacting me, Anthony-san.

Please tell me about the following items.

① Can you disclosure the sample test result of UVLO detection voltage (when VIN is lowered) in the same way?

② Can you disclosed VUVLO distribution and VUVP distribution as 3σ data in add sample test data conducted in other cases?

＜Because＞
From the customer's confirmation method occurred,
when VIN was lowered,After VOUT stops it says that latch will be applied and VOUT will not be output even if the power supply returns.
Therefore, it is necessary to explain the range (limit) where the input voltage operates after looking at the distribution of VUVLO and the distribution of VUVP.

I'm sorry, but aware of the difficulty of presenting data from the manufacturers,
but can you please support(help) somehow?

Best regards,
Masumi Sekiguchi

Hi Masumi-san,

① Can you disclosure the sample test result of UVLO detection voltage (when VIN is lowered) in the same way?
UVLO high: 3.691V, 3.7277V, 3.781V
UVLO low: 3.459V, 3.492V, 3.538V

② Can you disclosed VUVLO distribution and VUVP distribution as 3σ data in add sample test data conducted in other cases?
I could not find data in our database. Need to align with my colleagues to check whether they have.

Thank you for the answer, Anthony-san.

＞② Can you disclosed VUVLO distribution and VUVP distribution as 3σ data in add sample test data conducted in other cases?
＞I could not find data in our database. Need to align with my colleagues to check whether they have.
⇒ Can you confirm it?

Could you help me?

Masumi Sekiguchi

Please let me post to confirm the situation.

①Can you deal with the following additionally?

①-1：Can you disclosure the sample test result of Hi-Side FET ON resistanse,too?

①-2：Do you have the following test data?

(Please disclose if you have it)

※Test contents：The actual value of the input voltage when the input is lowered from 12 V and the output stops.

②Could you disclosed 3σ data in add sample test data conducted in other cases?

※Target data：VUVLO / VUVP / Hi Side FET Ron / The test data described in "①-2"

Could you help my customer?

Please inform the situation about the previous post.

Hi Masumi-san,

Sorry for the late. Tried to find from other documents and found one that includes the average test value its sigma data within. Could you let me know your email? It is easier to paste all of them for you. Thanks!

I agree it, please.

But, are there passages that we only interact at private?
I will post my e-mail address there.