[FAQ] AM62L, AM64x, AM243x (ALV, ALX) Custom board hardware design – ADC0 design guidelines

Hi Board designers, 

Thank you for the query.

AM64x/ AM243x (ALV)

1. Supported ADC resolution and channels

The processor family supports 1 × 12-bit ADC, up to 4 MSPS, and 8 multiplexed analog inputs. See the device-specific silicon errata (advisory i2287) for guidance on using SR2.0 processor on existing board or recommendations for a new custom board design. For more details, see the General Connectivity Peripherals section in the Peripherals chapter of the device specific TRM. Note that the processor family ADC inputs are not fail-safe. Do not apply external inputs before the processor supplies ramps.

2. Guidelines for using ADC peripheral

See the device-specific silicon errata (advisory i2287) for guidance on using SR2.0 processor on existing board or recommendations for a new custom board design.

 Note that the processor family ADC inputs are not fail-safe. Do not apply external inputs before the processor supplies ramps and are stable.

Refer pin Pin Connectivity Requirements section for connecting the ADC inputs when complete ADC is not used or any of the ADC inputs are not used 

3.ADC0 input range 

The ADC0 module supports the below ADC reference pins

ADC0_REFN -   ADC0 Negative Reference J16
ADC0_REFP  -  ADC0 Positive Reference J15

Additionally the ADC0 modules includes VDDA_ADC0 ADC0 analog supply

ADC12B Electrical Characteristics describes the allowed range ADC range VADC0_VREFP and VADC0_VREFN

4.ADC inputs used as GPI 

The ADC inputs are connected to the AM64x/AM243x (ALV) GPIO1 module when configured to operate as general-purpose inputs (GPI). The assignment of each ADC0 pin to the GPIO1 module is defined in the ADC0 Signal Description table found in the datasheet.

These inputs are able to perform the same input function as any other GPIO1 input. Please read the GPIO sections in the TRM to understand the capabilities of these inputs.

AM243x (ALX)

1. Supported ADC resolution and channels

The processor family supports 1 × 10-bit ADC, up to 4 MSPS, and 8 multiplexed analog inputs. See the device-specific silicon errata (advisory i2287) for guidance on using SR2.0 processor on existing board or recommendations for a new custom board design. For more details, see the General Connectivity Peripherals section in the Peripherals chapter of the device specific TRM. Note that the processor family ADC inputs are not fail-safe. Do not apply external inputs before the processor supplies ramps.

2. Guidelines for using ADC peripheral

See the device-specific silicon errata (advisory i2287) for guidance on using SR2.0 processor on existing board or recommendations for a new custom board design.

 Note that the processor family ADC inputs are not fail-safe. Do not apply external inputs before the processor supplies ramps and are stable.

Refer pin Pin Connectivity Requirements section for connecting the ADC inputs when complete ADC is not used or any of the ADC inputs are not used 

3. .ADC0 input range 

VADC0_VREFP (1) Positive Reference Voltage 1.71 1.89 V
VADC0_VREFN (1) Negative Reference Voltage VSS V

ADC10B Electrical Characteristics (ALX package) describes the allowed ADC range 

4.ADC inputs used as GPI 

The ADC inputs are connected to the AM243x  (ALX) GPIO1 module when configured to operate as general-purpose inputs (GPI). The assignment of each ADC0 pin to the GPIO1 module is defined in the ADC0 Signal Description table found in the datasheet.

These inputs are able to perform the same input function as any other GPIO1 input. Please read the GPIO sections in the TRM to understand the capabilities of these inputs.

AM62L 

1. Supported ADC resolution and channels

1x 12-bit Analog-to-Digital Converter (ADC)
– 10 bits of effective resolution (ENOB ≅ 10)
– Up to 4MSPS
– 4x analog inputs (time-multiplexed)

2. Guidelines for using ADC peripheral

Note that the processor family ADC inputs are not fail-safe. Do not apply external inputs before the processor supplies ramps and are stable.

Refer pin Pin Connectivity Requirements section for connecting the ADC inputs when complete ADC is not used or any of the ADC inputs are not used

3.ADC0 input range 

VADC0_VREFP Positive Reference Voltage = VDDA_ADC0

VADC0_VREFN Negative Reference Voltage = VSS

The ADC0 module does not support separate VADC0_VREFP and VADC0_VREFN pins 

4.ADC inputs used as GPI 

Not supported 

Regards,

Sreenivasa

Hi Board designers, 

Additional information on AM64x input range 

(34) AM6422: External Analog Reference for ADC0 - Processors forum - Processors - TI E2E support forums

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1304300/faq-am6442-adc0_dig_test-0-7-when-a-digital-inputs-can-these-eight-be-considered-as-main-gpio-and-or-interrupt-inputs-at-1-8v-logic

External Analog Reference for ADC0

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1433807/am6422-external-analog-reference-for-adc0/5499688#5499688

AM6442: Configuring AM6442 ADC0 pins as GPI.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1498583/am6442-configuring-am6442-adc0-pins-as-gpi

 Overvoltage at ADC input

TI expects the system designer to design their product to operate withing the Recommended Operating Condition (ROC) limits, not the Absolute Maximum Rating limits. See table note #1 associated with the Absolute Maximum Rating table.

Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Section 6.4, Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

You should not be using the limits defined in the Absolute Maximum Rating table for designing normal operating conditions. Applying a potential outside of the ROC limits has a chance of damaging the AM64x device. The ROC max for VDDA_ADC0 is 1.89V and the ROC max for any AIN[7:0] is the same potential that is applied to VDDA_ADC0. There is a chance you will damage the device if you exceed these ROC limits for any period of time. 

AM64x has internal ESD clamp diodes on each of the AIN[7:0] pins. These internal clamps must be considered because they turn on when the applied voltage exceeds the limits defined in the "Steady-state max voltage at all other IO pins" parameter defined in the Absolute Maximum Rating table.

Note: The internal ESD protection circuits were only designed to protect the device during handling, before and during PCB assembly. These clamps are not capable of protecting the device from system-level ESD events, which can have much higher energy levels that what is encountered during device handling. Therefore, the system designer is expected to use external ESD protection circuits if it necessary to protect AM64x from system-level ESD events.

The device IBIS model should represent what you can expect to see when looking into one of the ADC AIN[7:0] pins.

AM2434: AM24x ADC0 Measurement at AIN7

(+) AM2434: AM24x ADC0 Measurement at AIN7 - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1500190/am2434-am24x-adc0-measurement-at-ain7

Regards,

Sreenivasa

Hi Board designers, 

Additional information on AM641x ADC connections:

In the Device Comparison table AM6412 and AM6411 does not support ADC. Is there a connection recommendation for the processor ADC supplies and ADC inputs?

The recommendation is to follow the recommendations as per Pin Connectivity Requirements

Regards,

Sreenivasa

HI Board Designers, 

Inputs related to ADC connections for AM64x:

Observation of AM64x schematics being reviewed:

Query 1:

SOC ADC interface: 

Power supplies that are available before SOC supplies are available are connected to ADC. SOC ADC inputs are not fail-safe. No inputs are recommended or allowed to be applied before SOC power ramps

 Customer comments:

Does that mean that we cannot measure voltage such as V0P85_CORE, V1P8_MPU_ANALOG, V1P1_LPDDR4 V3P3_MPU_IO, V5P25_SMPS and +16V since they are available before the SOC are power up? As you can see, all these voltage already go thru voltage divider with a small cap that will slowly ramp up the circuit, will that helps to “protect” the ADC internal circuit. Isn’t these ADC input high impedance? Is there a ADC input tolerance? 

Expert inputs

The answer to the above question is addressed by the “Steady-state max voltage at all other IO pins” parameter found in the Absolute Maximum Ratings table.

 They need to implement a switch or clamp circuit on each ADC input signal that blocks any potential from being applied to any of the ADC0_AIN[7:0] inputs before the supplies powering VDDA_ADC and ADC0_REFP are valid.  The rate of charge of their filter capacitors and the power supply ramp rates have too much variability for the capacitor delay option to be a robust solution. Without blocking the potential, there will be some potential applied to the ADC inputs as soon as these early power supplies begin to ramp and this is not allowed if the potential applied ever exceeds the Absolute Maximum Ratings limits, which is shown below.

Query 2:

ADC reference is not connected. Verify the ADC reference connection. Connect to ground and 1.8V reference supply

Expert input:

Suggest reading the note below if the ADC0_REFP and ADC0_REFN pins were not connected.

The ADC0_REFP and ADC0_REFN reference inputs are analog inputs which must be treated like high transient power supply rails.
ADC0_REFN is expected to be connected directly to the PCB ground plane along with all other VSS pins, and ADC0_REFP is
connected to a power source capable of providing at least 4 mA of current. ADC0_REFP can be connected to the same power source as VDDA_ADC0 if the voltage tolerance of the supply provides an acceptable accuracy for the ADC reference. A high frequency decoupling capacitor must be connected directly to the ADC0_REFP and ADC0_REFN pins with vias and be placed in the ball array on the back side of the PCB.

Customer is monitoring 16V, 9V, 5V, 3.3V, 2.5V, 1.8V, 1.1V and 0.85V.

The question is would the 1.1V and 0.85V which ramps after the 1.8V ramp requires to be switched?

They need to make sure no input has a potential applied while the respective IO power supply is not valid.  This includes power-up and power-down sequencing of their power supplies.  The potential applied to an input can track the respective IO power supply, but it must not exceed the IO power supply by more than the limits defined in the Absolute Maximum Ratings table.

In regards to the ADC inputs cannot be applied before the ADC circuit is powered up by 1.8V (pin J15 and J16), I was thinking if it is possible to use a separate precision LDO to supply a 1.8V to J15 just for the ADC circuit so that this separated LDO can powered on before others voltage such as 3.3V,2.5V,1.8V,1.1 and 0.85V is properly powered up?

The ADC0_VREF is technically a input pin to the ADC and has the same power sequencing requirements as the AIN[7:0] pins.  However, the ADC0_VREF input must be treated like a power supply pin since it has high current transients and the voltage applied should not have a significant drop during the high current transients.  See the note inserted below.

So no, they are not allowed to apply a potential to the ADC0_VREF pin while the VDDA_ADC power rail is not valid.

 Regards,

Sreenivasa