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Original question:

TDA4VM: After builded MCU1_0, Run vision apps Demos for Display , IPC error occurs .

TDA4VM: Sgmii mode configuration problem

HONGRUN ZHAO
Intellectual 555 points
Part Number: TDA4VM
Other Parts Discussed in Thread: DRA829,

Device: TDA4

SDK Vesion: sdk7_03

i have some problem for  configured the sgmii

i read the Technical Reference Manual
 << J721E DRA829/TDA4VM Processors Silicon Revision 1.1 Texas Instruments Families of Products>>

5.1.3.4.62 CTRLMMR_SERDES1_LN0_CTRL Register ( Offset = 4090h) [reset = 0h] 

1-0 LANE_FUNC_SEL R/W 0h Selects the SERDES1 lane0 function
0h - Enet Switch Q/SGMII Lane 3
1h - PCIe1 Lane 0
2h - For USB1 lane swap. Select this if USB1 was implemented with
Type C connector
3h - ICSS_G1 SGMII Lane 0

5.1.3.4.63 CTRLMMR_SERDES1_LN1_CTRL Register ( Offset = 4094h) [reset = 0h]

1-0 LANE_FUNC_SEL R/W 0h Selects the SERDES1 lane1 function
0h - Enet Switch Q/SGMII Lane 4
1h - PCIe1 Lane 1
2h - USB1
3h - ICSS_G1 SGMII Lane 1

it look's like SERDES1 lane3 and lane4 can be used at the same time , but then i configured lane3 with 

ENET_MAC_SGMIIMODE_SGMII_AUTONEG_MASTER lane4 ENET_MAC_SGMIIMODE_SGMII_AUTONEG_SLAVE
 
the sgmii lane3 and lane4 all fail. if i use one of SERDES1’s lane it's ok
so in the same SERDES  the two modes Can't be used together,isn't it?
in the same SERDES if i want use two lane which mode can be configured toghter
 Thanks
  • 0
    TI__Mastermind 37435 points

    Hi,

    Can you provide your use case ? How many ethernet ports you want to use with SGMII, how many PCIe and USB ?

    Regards

    Vineet

  • 0 in reply to Vineet Roy
    Intellectual 555 points

    hi Vineet Roy

     thanks for replay

    i use serdes1 two SGMII,SGMII3 SGMII4 , the sgmii3 and sgmii4 is mac to mac

    one pcie in serdes2

    one dp in serdes4

    one usb

  • 0 in reply to Vineet Roy
    Intellectual 555 points

    hi Vineet

        my problem is sgmii3 and sgmii4 ，Can be configured to ENET_MAC_SGMIIMODE_SGMII_AUTONEG_MASTER at the same time？

    in sdk 7.3 rtos + linux if i configured the sgmii3 and sgmii4 to ENET_MAC_SGMIIMODE_SGMII_AUTONEG_MASTER  at the same time，

    ioctl has some error like next 
    [MCU2_0] 73.818903 s: EnetMod_ioctl: cpsw9g.cpts: Failed to do IOCTL cmd 0x0101030c: -14
    [MCU2_0] 73.818946 s: EnetPer_ioctl: cpsw9g: Failed to do IOCTL cmd 0x0101030c: -14
    [MCU2_0] 73.818981 s: Enet_ioctl: cpsw9g: IOCTL 0x0101030c failed: -14
    [MCU2_0] 74.028823 s: CpswCpts_ioctl: Failed to lookup for event: -14

    but if i use one of sgmii it's no error

  • 0 in reply to HONGRUN ZHAO
    TI__Mastermind 37435 points

    Hi,

    > my problem is sgmii3 and sgmii4 ，Can be configured to ENET_MAC_SGMIIMODE_SGMII_AUTONEG_MASTER at the same time？

    I will double check but I don't think you can have both sides set to master, as per the TRM only one side must be master for a direct connection.

    Regards

    Vineet

  • 0 in reply to Vineet Roy
    Intellectual 555 points

    hi vineet

    thanks for your replay 

    if i need two sgmii_autoneg_master mode ,i need two serdes for this ?

    like serdes0 SGMII2 SET TO ENET_MAC_SGMIIMODE_SGMII_AUTONEG_MASTER 

           serdes1 SGMII4 set to ENET_MAC_SGMIIMODE_SGMII_AUTONEG_MASTER 

    isn't it?

  • 0 in reply to HONGRUN ZHAO
    TI__Mastermind 37435 points

    Hi,

    I don't think it's about SERDES, ethernet requires connection in a master-slave relationship. So one link partner is master and other partner is slave.

    Regards

    Vineet

  • 0 in reply to Vineet Roy
    Intellectual 555 points

    hi vineet

    Maybe my description is wrong. I mean that I need to use two sgmii's mac2mac mode. When I use sgmii4's mac2mac mode and configure it as master, then sgmii3 can't be used as the master mode of mac2mac. Is this right？

    When I set up using the following schematic , the ioctl has error like this
    [MCU2_0] 73.818903 s: EnetMod_ioctl: cpsw9g.cpts: Failed to do IOCTL cmd 0x0101030c: -14
    [MCU2_0] 73.818946 s: EnetPer_ioctl: cpsw9g: Failed to do IOCTL cmd 0x0101030c: -14
    [MCU2_0] 73.818981 s: Enet_ioctl: cpsw9g: IOCTL 0x0101030c failed: -14
    [MCU2_0] 74.028823 s: CpswCpts_ioctl: Failed to lookup for event: -14

     

    Regards

  • 0 in reply to HONGRUN ZHAO
    TI__Mastermind 37435 points

    Hi,

    I see what you mean, you cannot configure two SGMII Masters on the device at the same time.

    What is the exact IOCTL command you are using ?

    Regards

    Vineet

  • 0 in reply to Vineet Roy
    Intellectual 555 points

    hi vineet

    thanks for your replay 

    > you cannot configure two SGMII Masters on the device at the same time.

    it's means a pcs tda4 only can configure one SGMII with master mode? if i want connect another board i must use sgmii whit phy?

    I haven't used the IOCTL command yet. The error is  MCU2 _0 print when  run vision_ app_init.sh

  • 0 in reply to HONGRUN ZHAO
    TI__Mastermind 37435 points

    Hi

    HONGRUN ZHAO said:
    it's means a pcs tda4 only can configure one SGMII with master mode? if i want connect another board i must use sgmii whit phy?

    No, it's not a statement from me, I was only trying to rephrase your problem.

    I am not aware of any such limitation. I will check and let you know.

    Regards

    Vineet

  • +1 in reply to Vineet Roy
    TI__Expert 3075 points

    Any port can be configured for SGMII based on the SOC SERDES mux registers.

    A SGMII can communicate between a master and slave in auto-negotiate, or both ends can be configured into master without SGMII.

    Auto-Negotiate mode:

    That is Device A  SGMII_Mr_Adv_Ability = 0x9801 and sgmii_Control = 0x0021 and Device B SGMII_Mr_Adv_Ability = 0x1 and sgmii_Control = 0x1 for auto-negotiate between Device A and Device B.

    Force Line mode:

    Or both sides could be SGMII_MR_ADV_ABILITY = 0x9801, and SGMII_CONTROL = 0x0020

    You should look at the WIZ_Px_ALIGN_RX_DELAY should be non-zero and steady. If Zero, something fundamental, lane not programmed, incorrect IP muxing, incorrect PLL reference clock. If it is changing, check wiz_standard_mode should be zero, there was a boot issue that set standard_mode to 3 which miss-programs the SERDES for SGMII.

    If it links, but there are CRC errors, it could be that the SERDES differential pins are swapped, there is a polarity flip in the program interface, but there was an error in the code that prevented it from staying that way. Make sure you have the latest SDK.