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TDA4VM: HOW TO CHECK MICRON LPDDR4 REGISTER SETTING

yutai li
Intellectual 620 points
Part Number: TDA4VM

Hi TI Support Team

Do you know hoe to read the micron LPDDR4 register setting from UBOOT or LINUX. 

Because we want to double check the Vref CA voltage is correct or not with your provide LPDDR4 config tools. From your tools the CA VREF =25.6% of VDDQ. 

That means the register in Micron LPDDRE should be 1 001001b. 

But i dont know how to read the register from TDA4 UBOOT or LINUX command. 

  • 0 in reply to yutai li
    TI__Mastermind 34690 points

    Hi,

    There is no command to read the DRAM registers from u-boot or Linux by default. There may be an existing function in the R5 bootloader that could be leveraged, but I do not know for sure. (will need to investigate)

    Note that VREF is trained during the initialization, so the final value will vary. My understanding is that the PI MR12 parameters (on processor side) should be updated with the value found from training. Would this satisfy your objective?

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Intellectual 620 points

    Hi Kevin

    1. Please help provide tool or command from R5 for DDR MODE REGISTER READ (MRR) , We need know the final CA/DQ Vref value from MR12 (MT53D1024M32D4DT-046.)

    2. I want to double confirm the CA/DQ Vref value will be update by TDA4 controller during initialization ?

    3. If not: do we need update the value from default setting as show in below. 

    4. If Yes: how to know the final CA/DQ Vref value after TDA4 training to update it. 

    5. We meet some issue when TDA4 LPDDR working at 4266Mbps, So we want to know if we need optimize Vref value. 

    Thanks

    Yutai

  • 0 in reply to yutai li
    TI__Mastermind 34690 points

    Hi,

    I am closing this thread as the issue was resolved via email. The issues that were being observed were resolved by making the following  register changes to the DDRSS registers:

    Bits[7:0] were changed from 7 to 6, as shown below:

    #define DDRSS_PHY_33_DATA 0x0C002006

    #define DDRSS_PHY_289_DATA 0x0C002006

    #define DDRSS_PHY_545_DATA 0x0C002006

    #define DDRSS_PHY_801_DATA 0x0C002006