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Original question:

TDA4VM: LPDDR4 training issue

TDA4VM: TDA4VM: LPDDR4 training issue for 3733 Micron chip

user5296716
Prodigy 70 points
Part Number: TDA4VM

We met exactly the same issue with https://e2e.ti.com/support/processors-group/processors/f/processors-forum/901244/tda4vm-lpddr4-training-issue

as we decrease LPDDR4 to 3200MT/s, everything works well.  The Micron chip is MT53D1024M32D4DT-046AUT:D

the ddrss register config is as attachedJacinto7_DDRSS_RegConfigTool_micron3733-hantao0801.rar

On very few board it works well, and on most boards, U-Boot still hangs when jumping from SRAM to DDR RAM,

If we do  memtest from R5 core, after the initializaiton, the memory address shows A5A5A5A5, but for some address it shows XXA5A5A5A5, XX maybe 00,24,85 etc.

It means only higher bytes error occurs. Could TI help to give some suggestion on DDR training register config or some other advices?  Thanks

Jacinto7_DDRSS_RegConfigTool_micron3733-hantao0801.rar

  • 0
    TI__Mastermind 34930 points

    Hi,

    This is being discussed internally. Tao will provide a 16-bit configuration to try.

    Thanks,
    Kevin

  • 0 in reply to Kevin S
    Prodigy 70 points

    As discussed, the 16bit configuration need to be test under linux,  at present if we can't boot successfully, 16bit test couldn't be performed.

    And I would like to update some new status

    1. Under 3733 mode, Once I modify the write DQ leveling pattern from 7 to 4 which is 0111 to 0100, I got most boards boot up successfully, but still has failure rate about 3/200,.

    2. 4266 configuration fail with write DQ leveling pattern from 7 to 4 or any other configuration

    Is there any more suggestion? thanks

  • 0 in reply to user5296716
    TI__Mastermind 34930 points

    Hi,

    I was previously informed that changing the write DQ leveling pattern from 7 to 6 did NOT improve results at 3733. I am surprised to hear that changing the pattern from 7 to 4 does help, but 7 to 6 does not help. 

    Can you please confirm the results at 3733 when write DQ leveling pattern = 6?

    #define DDRSS_PHY_33_DATA 0x0C002006
    #define DDRSS_PHY_289_DATA 0x0C002006
    #define DDRSS_PHY_545_DATA 0x0C002006
    #define DDRSS_PHY_801_DATA 0x0C002006

    Thanks,
    Kevin

  • 0 in reply to Kevin S
    Prodigy 70 points

    I tried the  DQ leveling pattern 7 to 6, and I confirmed it hadno big improvement.

  • +1 in reply to user5296716
    TI__Mastermind 34930 points

    Hi, can you also try this experiment:

    • For below registers, change the '20' to a '40' as shown below

    #define DDRSS_PHY_32_DATA 0x10400000
    #define DDRSS_PHY_288_DATA 0x10400000
    #define DDRSS_PHY_544_DATA 0x10400000
    #define DDRSS_PHY_800_DATA 0x10400000

  • +1
    Prodigy 70 points

    Have tried this modification, and it turned out to be no improvement.

    #define DDRSS_PHY_32_DATA 0x10400000
    #define DDRSS_PHY_288_DATA 0x10400000
    #define DDRSS_PHY_544_DATA 0x10400000
    #define DDRSS_PHY_800_DATA 0x10400000

    and we produced another build which changed FR4 material to S1000-2, problem solved.