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Original question:

AM3352: Inquiries about DDR3(4GB) implementation

AM3352: Output status(Low/High/floating) of the DDR_A14 and DDR_A15 pins

Takayuki Miyazaki
Genius 10120 points
Part Number: AM3352

This thread is related to https://e2e.ti.com/support/processors-group/processors/f/processors-forum/991788/am3352-inquiries-about-ddr3-4gb-implementation

Hi Experts,

I received customer's further question at this time again. Customer would like to confirm the output status(Low/High/floating) of the DDR_A14 and DDR_A15 pins when SDRAM CONFIG register was configured like the attached file(0574.AM3352_SRAM_CONFIG_REGISTER.zip). DDR_A14 and A15 are not used as Row addresses. (reg_row-size: DDR_A13 ~ DDR_A0). Although A14 and A15 state can be controlled using internal pull up/down resistors configured in the ddr_cmdX_ioctrl registers, it seems customer would like to know this output status when ddr_cmdX_ioctrl registers are default. I’m sorry to bother you.

Can I have your advice/comments on this, please?

Best regards,

Miyazaki