• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Subscribers 98 subscribers
  • Views 599 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TMS320C6657: Hold Time of POR, RESETFULL, or RESET

TMS320C6657: Reset by RESETFULL does not work properly

O.H
Mastermind 6350 points
Part Number: TMS320C6657
Other Parts Discussed in Thread: TMS320C6652, , TMS320C6655

(Sorry. The exact part number is TMS320C6652.)

Hi experts,

Q1:If the behavior of the reset by RESETFULL and the reset when the power is turned on again is different, should we suspect the influence of a device other than the DSP on the board?

A customer wants to have a function to restart the DSP with the power on state by checking the time elapsed with another device when the DSP software operation stops due to some trouble (static electricity, etc.) in the board circuit (hereinafter referred to as WDT).They are actually trying to run WDT on the board to reboot the DSP in the power-on state, but when it reboots, the DSP operation seems to be stuck (the software is not running) and the cause is unknown.

They have tried asserting → deasserting RESETFULL to reboot, but the above behavior. So they tried asserting POR and RESETFULL at the same time → deasserting POR only → deasserting RESETFULL, but the situation is the same. The time to assert POR is about 10msec, and RESETFULL is deasserted about 5msec after POR is deasserted (as a result, the time to assert RESETFULL is about 15msec).

Their circuit boots from external ROM via SPI, and the BOOTMODE signal setting seems to be correct at the time of RESETFULL deassertion. When the power is turned off and on, and RESET is asserted and deasserted, the DSP is operating.

Q2:Is it necessary to assert up to RESET when power is turned on? If they do assert to RESET, is it correct to assume that reasserting RESET to deassert in power-on state does not cause BOOTMODE latch, although there is no problem since the behavior is described in "6.5.2 Hard Reset"?

The function of WDT itself does not work if the software is working properly. However, if the DSP software does not work due to some problem, the WDT will work. So, in extreme cases, if the software does not work even after the DSP is rebooted (e.g. ROM failure), the WDT (every few seconds) will work again and again. Doesn't this affect the failure of the DSP itself?

I am concerned that this may violate the contents of the data sheet "6.3.1.3 Prolonged Resets".

6.3.1.3 Prolonged Resets

Holding the device in POR, RESETFULL, or RESET for long periods of time will affect the long term reliability of the part. The device should not be held in a reset for times exceeding 1 hour and should not be held in reset for more the 5% of the time during which power is applied. Exceeding these limits will cause a gradual reduction in the reliability of the part. This can be avoided by allowing the DSP to boot and then configuring it to enter a hibernation state soon after power is applied. This will satisfy the reset requirement while limiting the power consumption of the device.

Best regards,
O.H

  • 0
    Mastermind 6350 points

    Hello,

    I'm sorry to rush you. What is the situation?

    The customer needs answers, so it would be helpful if you could share your progress with us.

    Best regards,
    O.H

  • 0 in reply to O.H
    TI__Guru* 84005 points

    O.H.

    I do not understand all your queries completely, but want to make sure you have looked at the following usage note and the timing requirements

    https://www.ti.com/lit/er/sprz381c/sprz381c.pdf

    Usage Note 6 POR and RESETFULL Sequence Usage Note Revision(s) Affected: 1.0 Details: For boot configuration pins to be latched correctly, during the power sequencing and reset control for chip initialization, RESETFULL must be held low for a period after the rising edge of POR but may be held low for longer periods if necessary. The configuration bits shared with the GPIO pins will be latched on the rising edge of RESETFULL and must meet the setup and hold times. Timing requirements are specified in the device-specific data manual, TMS320C6655/57 Multicore Fixed and Floating-Point Digital Signal Processor, TMS320C6652/54 Multicore Fixed and FloatingPoint Digital Signal Processor

  • 0 in reply to Mukul Bhatnagar
    Mastermind 6350 points

    Hi Mukul-san,

    Thank you for your reply.

    Mukul Bhatnagar said:
    Usage Note 6 POR and RESETFULL Sequence Usage Note Revision(s) Affected: 1.0 Details: For boot configuration pins to be latched correctly, during the power sequencing and reset control for chip initialization, RESETFULL must be held low for a period after the rising edge of POR but may be held low for longer periods if necessary. The configuration bits shared with the GPIO pins will be latched on the rising edge of RESETFULL and must meet the setup and hold times. Timing requirements are specified in the device-specific data manual, TMS320C6655/57 Multicore Fixed and Floating-Point Digital Signal Processor, TMS320C6652/54 Multicore Fixed and FloatingPoint Digital Signal Processor

    The customer holds RESETFULL low for 5msec after the rising edge of POR. Since the input clock to SYSCLK1 is 100MHz, I think the requirements of the datasheet are well met.

    The problem this time is that the system is not being reset with power supplied. If they perform a High/Low operation on the RESETFULL pin only, they will not be able to reset successfully. I double-checked the datasheet, and it may be that the method is not correct for what they want to achieve.

    If they want to reset the system with power being supplied, they need to perform operations on the RESET pin only (6.5.2 Hard Reset), is this correct?

    If they do "6.5.2 Hard Reset", will the contents of the boot configuration pins be the same as those latched by the first power-on reset (6.5.1 Power-on Reset)?

    Best regards,
    O.H

  • 0 in reply to O.H
    Mastermind 6350 points

    Hello,

    Sorry. The problem was resolved on the customer side.

    The cause was that PCIESSEN was not set to Low during the reboot. Now we are able to reboot by operating RESETFULL only from Low to High.

    Please let me check just in case. Is there any problem if they repeatedly operate RESETFULL from Low to High while the power is on?

    Best regards,
    O.H

  • 0 in reply to O.H
    TI__Guru* 84005 points

    O.H san

    Good to hear that the issue is resolved, as I was going to refer to the posts 

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/855865/tms320c6652-boot-mode-setting?tisearch=e2e-sitesearch&keymatch=PCIESSEN#

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/891006/tms320c6652-spi-boot-mode/3341351#3341351

    and Table 8-1 in the datasheet. 

    I do not understand why they would want to assert RESETFULL repeatedly? Not something that we have tested or can comment much on. 

    Some additional clarifications on PORz versus RESETFULLz versus RESETz:

    • PORz and RESETFULLz are absolute digital resets.  All digital circuits are reset synchronously by these inputs.
    • PORz also has HHV control which is asynchronous.  It must be low whenever any power input is not valid.
    • Proper sequencing of RESETz, PORz and RESETFULLz as shown in the DM is required for proper device wake-up.  Timing relative to clocks and supply ramping is important.
    • RESETFULLz as shown in the sequencing latches the boot configuration pins.  All latched inputs must be at the required level EVERY time the boot configuration is latched.
    • Since BOOT configuration pins are muxed pins, they must be at the proper state when latched.  Logic must be implemented that monitors RESETSTATz and restores the proper input levels for latching.
    • Assuming boot configuration pins are properly managed, RESETFULLz will reset the device, properly latch the pins and wake in the same mode reliably.
    • RESETz is a software-defined reset and allows for programmable reset-isolation.  It does not latch the boot configuration pins.  It also does not reset the DEVSTAT register that can be written by software.
  • 0 in reply to Mukul Bhatnagar
    Mastermind 6350 points

    Hi Mukul-san,

    I'm sorry. I translated the customer's question incorrectly.

    The word "repeatedly" is an extreme example. What I would like to confirm now is how to do a complete reset (Power-on Reset) when the power is stable and the device is working normally.

    Which of the following is the correct way to do a reset when the power is stable? (or Which is it recommended?)

    1. Change RESETz, PORz, and RESETFULLz to Low. Next, change RESETz to High. Next, change PORz to High, and then change RESETFULLz to High.
    2. Change PORz and RESETFULLz to Low. Then change PORz to High and RESETFULLz to High.
    3. Change RESETFULLz to Low. Then change RESETFULLz to High.

    Best regards,
    O.H

  • +1 in reply to O.H
    TI__Guru* 84005 points

    Hello

    #3 is the recommended way. 

    Regards

    Mukul 

  • 0 in reply to Mukul Bhatnagar
    Mastermind 6350 points

    Hello,

    OK, I understood.

    Sorry for take your time. And thanks for your support!!

    Best regards,
    O.H