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C6457 SRIO board routing

Bryan Busacco
Expert 1215 points

 

 

With arespect to board layout on a design that includes the C6457 DSP, we have questions regarding SRIO BGA double trace escapes. There is a recommendation of 1.7mil traces spaced 1.7mils. Our circuit board  fabrication facility has been questioning of these values. (spru811a sheet 21 )

Does TI have a suggested PCB manufacturer in mind that can meet these numbers?

 

Also, spraay1a.pdf, sheet 5 Table 2 shows the suggested trace widths based on overall length. Could we use the 4mil trace width for a 2-4” run on one PCB, the signal will goes through two connectors, then use the 6mil trace width for a ~15” run on the motherboard PCB? (Both the 4mil and 6mil would be spaced such as to obtain 100 ohms differential impedance.)  

                Will there be any adverse affects if this method is employed?

 

Reference documents:

SPRU811a: http://focus.ti.com/lit/ug/spru811a/spru811a.pdf

SPRAAY1a:  http://focus.ti.com/lit/an/spraay1a/spraay1a.pdf

 

Thank you,

 

Bryan Busacco

  • 0
    TI__Mastermind 42545 points

    Brian,

    Although the diagram for double trace escape is provided as part of the spru811a document, it is not common practice to route more the one trace between balls with a spacing of 0.8mm.  If a 0.45mm pad is used with a 0.60mm solder mask opening there is a possibility that the edges of the trace will be exposed increasing the likelihood of manufacturing problems.  I would recommend that you use a 4mil trace with 4mil spacing and only run a single trace between pads.  In addition TI does not maintain a list of manufacturers capable of working with double trace escape. 

    There are two issues associated with the use of a narrower trace width for a portion of the SRIO run, loss and discontinuity at the point were the width changes.  The discontinuity is already present since the signal must travel through a connector therfore this isn't an issue in this case.  The loss for the short run mentioned shouldn't be significant since the length of the narrower trace is kept to a minimum.  The loss through the connector will be more significant then the loss due to the narrower trace so be sure that the connector used minimizes that loss. 

  • 0 in reply to Bill Taboada
    Expert 1215 points

    If we cannot escape route two traces between two 0.8mm BGA “pads” on an internal layer, then how would TI recommend routing these traces?

    -The 4mil trace width differential pairs will have to separate right away?

    - We need to maintain coupling between the traces as they separate and pass multiple other “pads” of different signal types?

    - Some pairs are buried 1,2 ,3 and 4 pins deep on the BGA.

    - Our current stack up requires trace widths of 4mils with a gap of 7mils to maintain a 100ohm differential impedance.

                    -When the signals separate, they will have a resulting gap of 27mils  for a length of at least 150mils.

                                    -What is the maximum length that these signals can separate?

    -How will this affect the SRIO signals at full speed?

    Thanks,

    Bryan Busacco

  • 0 in reply to Bryan Busacco
    TI__Mastermind 42545 points

    Hi Bryan,

    It's clear that the pin placement of the SRIO signals C6457 present some specific problems that were not covered in the serdes implementation guidelines.  I'm working on a document with some specific suggestions for the signal escape and routing of the SRIO on the C6457 which should be completed soon.  I will post it once I've run it past our design team.

  • 0 in reply to Bill Taboada
    TI__Mastermind 42545 points

    After discussing the issue of routing the C6457 with the SerDes experts within TI I've created the following guidelines for routing the SRIO signals for the C6457.

     

    serial rapidIO routing for C6457.pdf