Part Number: TMDS64GPEVM
Hi,
The GEL output seems to be stuck once I did the DDR initialization for AM64 CORTEX R5_0_0. See below:
MAIN_Cortex_R5_0_0: GEL Output: Running from R5
MAIN_Cortex_R5_0_0: GEL Output:
DDR not initialized with R5 connect.
Go to menu Scripts --> AM64 DDR Initialization -> AM64_DDR_Initialization_ECC_Disabled to initialize DDR.
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MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR4 Initialization is in progress ... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> ECC Disabled <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR controller programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR controller programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 0 programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 0 programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 1 programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 1 programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 0 programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 2 programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 1 programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 1 programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address slice 2 programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 2 programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> Set PHY registers for all FSPs simultaneously (multicast)... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_400MHz
MAIN_Cortex_R5_0_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set.
MAIN_Cortex_R5_0_0: GEL Output: Setting DDR4 frequency...
MAIN_Cortex_R5_0_0: GEL Output: Triggering start bit from PI...
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI initialization started... <<<---
MAIN_Cortex_R5_0_0: GEL Output: Triggering start bit from CTL...
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR CTL initialization started... <<<---
MAIN_Cortex_R5_0_0: GEL Output: Polling PI DONE bit...
MAIN_Cortex_R5_0_0: GEL Output: pi_int_status = 0x29C12001...
MAIN_Cortex_R5_0_0: GEL Output: - PI_INIT_DONE_BIT set: The power-on initialization training in PI has been completed.
MAIN_Cortex_R5_0_0: GEL Output: - PI_LVL_DONE_BIT set: The leveling operation has completed.
MAIN_Cortex_R5_0_0: GEL Output: - PI_DLL_LOCK_STATE_CHANGE_BIT set: A state change has been detected on the dfi_init_complete signal after initialization.
MAIN_Cortex_R5_0_0: GEL Output: - PI_RDLVL_GATE_DONE_BIT set: A read leveling gate training operation has been completed.
MAIN_Cortex_R5_0_0: GEL Output: - PI_RDLVL_DONE_BIT set: A read leveling operation has been completed.
MAIN_Cortex_R5_0_0: GEL Output: - PI_WRLVL_DONE_BIT set: A write leveling operation has been completed.
MAIN_Cortex_R5_0_0: GEL Output: - PI_VREF_DONE_BIT set: A VREF setting operation has been completed.
MAIN_Cortex_R5_0_0: GEL Output: - Not documented bit set.
MAIN_Cortex_R5_0_0: GEL Output: ctl_int_status = 0x00000008...
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