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AM5746: DDR3L SDRAM With ECC requirement

Part Number: AM5746

Hi Team 

AM5746 EMIF1 interface has ECC features. I prefer to have ECC features enabled in my project. 

As the processor AM5746 has inbuild ECC feature, can I have normal DDR3L memory devices without ECC?

Eg:

Case 1: AM5746 EMIF1 interface with IS43TR16256BL -- Normal DDR3L (Without ECC)

Case 2: AM5746 EMIF1 interface with IS43TR16256ECL - DDR3L with ECC

With the above 2 cases, will have ECC features enabled?

Please clarify. 

Regards

Prabhu

  • Hi,

    In order to use the ECC features of the AM5746 EMIF1, you need to connect a DDR memory to the DDR_ECC pins of AM5746. Normal JEDEC compliant DDR3L memories can be used for both the 32-bit EMIF data bus and the EMIF ECC bus. As an example, you may refer to the AM574 IDK: https://www.ti.com/tool/TMDSIDK574 

    The second link provided in your question leads to a questionnaire as opposed to a datasheet. I could not find the datasheet browsing ISSI's webpage. Note that using the ECC feature of the DRAM may require certain functionality of the controller (AM5746) which may not be supported by AM5746. 

    Best regards,
    Kevin

  • Hi Kevin, 

    Thanks for your inputs. 

    Case 1: Interfacing with External ECC mode . I can refer Industrial development kit

    Case 2: Interfacing with DDR3L memory with ON-chip ECC. (Need more explanation)

    No reference are available. I have attached the general block diagram and datasheet of On-Chip ECC memory. 

    Please suggest what would be the case if DDRECC_D0...D7, DDRECC_DQM and DDRECC_DQS left unconnected if we use On-Chip ECC  DDR3L memories. 

    Attached the datasheet and block diagram of on-Chip ECC memory.

    At high level does AM574x support on-Chip ECC architecture?

     43-46TR16256EC-85120ECL.RevB.pdf

  • Hi,

    No, the DDR3L memory with on-chip ECC is not supported.

    According to section 10 of the DDR3 datasheet, ECC is disabled by setting MR3[5] = 0. 

    Please refer to section 16.3.4.7.2 DDR3 SDRAM Initialization of the AM5746 TRM which states that MR3 will be programmed to 0x0 during initialization. 

    https://www.ti.com/lit/pdf/spruih8 

    Best regards,
    Kevin