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TDA4VM: ISP

xin alex
Intellectual 506 points
Part Number: TDA4VM

Hi TI expert；

     TDAAvM device 

     VPAC module support  RAW10 image process  On <VHWA_Overview.pdf>;When I process Raw10 image， error occurred;

Logs As Flow:

                   [MCU2_0]   5169.146715 s:  VX_ZONE_ERROR:[tivxVpacVissCreate:599] Failed to set Params in driver

My config parameters as flow:

obj->raw_params.width = 1920;
obj->raw_params.height = 1440;
obj->raw_params.num_exposures = 1;
obj->raw_params.line_interleaved = vx_false_e;
obj->raw_params.format[0].pixel_container = TIVX_RAW_IMAGE_16_BIT;
obj->raw_params.format[0].msb = 9;
obj->raw_params.format[1].pixel_container = TIVX_RAW_IMAGE_8_BIT;
obj->raw_params.format[1].msb = 7;
obj->raw_params.format[2].pixel_container = TIVX_RAW_IMAGE_P12_BIT;
obj->raw_params.format[2].msb = 11;
obj->raw_params.meta_height_before = 0;
obj->raw_params.meta_height_after = 0;        

Do you some advise for me ? 

I searched likely problems On E2E,  I found that RAWFE can convert RAW10  to RAW12 By shift 2.

Where Can I get this demo code ?

  • 0
    TI__Guru**** 454515 points

    Hi,

    I think i know why it returning error. Can you make small change and try it out?

    In the API tivxVpacVissSetInputParams, in the file ti-processor-sdk-rtos-j721e-evm-07_03_00_07\tiovx\kernels_j7\hwa\vpac_viss\vx_vpac_viss_target.c, can you make below change and try it out?

    switch (raw_img_desc->params.format[0U].pixel_container)
    {
    vx_uint32 msb;
    case (vx_enum)TIVX_RAW_IMAGE_8_BIT:
    fmt->ccsFormat = FVID2_CCSF_BITS8_PACKED;
    break;
    case (vx_enum)TIVX_RAW_IMAGE_16_BIT:
    msb = raw_img_desc->params.format[0U].msb;
    if(msb < 7U)
    {
    VX_PRINT(VX_ZONE_ERROR, "Invalid Format \n");
    /* do nothing */
    }
    else if (msb == 15U)
    {
    fmt->ccsFormat = FVID2_CCSF_BITS16_PACKED;
    }
    else if ((msb <= 12u) && (msb > 8u))
    {
    fmt->ccsFormat = FVID2_CCSF_BITS12_UNPACKED16;
    }
    else
    {

    Regards,

    Brijesh

  • 0
    Intellectual 506 points

    Hi Ti expert，

         If I do this way "if ((msb <= 12u) && (msb > 8u))"

         ISP process  image By RAW12, But My image is raw10;

          BIT11,BIT10   is invalid data， This can  reduce image quality.

  • 0 in reply to xin alex
    TI__Guru**** 454515 points

    Yes, input configuration is 12bit even in this case, then you could use mask and shift block in isp to get 10bit data.

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 506 points

    Hi Ti expert，

       

        Where Can I get mask and shift demo ?  and I found  viss Module can process RAW10 by VHWA_Overview doc, But TI SDK can not support it，

    VISS RAW10 image function will  support in future ？

        Thks !

  • 0 in reply to xin alex
    TI__Guru**** 454515 points

    Yes, raw10 is supported on HW, but not validated in SDK. With the above changes, you will be able to use raw10 bit image.

    For changing mask and shift parameters, please refer to pwl parameters in decompanding block.

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 70 points

    Hi Brijesh,

    We are facing the same issue as described in the question. 

    Can you provide the details of the required modifications to mask and shift parameters and the location where to apply those in order to use raw10 bit image?

    Thank you and Best Regards,
    Max

  • +1 in reply to Max Hartmann
    TI__Guru**** 454515 points

    Hi Max,

    In this case, the input is still stored in the 16bit container and we use the patch above to configure VISS to read 12bit data. 

    In decompanding block, there is an option to mask and shift the input data. We can use it to get 10bit data from the input 12bit data. These fields can be enabled even without enabling decompanding block. 

    In this case, you could set the mask to 0x3FF and shift to 0 to get back 10bit input data and then further process 10bit data in the ISP. 

    I think in the current VISS node implementation, we set the mask and shift values only if decompanding block is enabled, in the API tivxVpacVissDccMapPwlParams in the file ti-processor-sdk-rtos-j721e-evm-07_03_00_07\tiovx\kernels_j7\hwa\vpac_viss\vx_vpac_viss_target_dcc.c. Can you try changing these parameters?

    Regards,

    Brijesh