Engineering: The PCB board is designed with 10-layer through holes, and the LPDDR4 section has encountered some problems.
Here are 2 options:
Option A: Reference design for TDA4VMid layer 10, Allegre can be opened, but conversion to PDAS 9.5 (suffix .PCB) was unsuccessful.
Option B: Reference design for TDA4VMid 16-layer board, conversion to PADS 9.5 successful. For the LPDDR4 trace section, the design is compressed to a 10-layer board (the trace remains the same), placed at L3, L5, L7, L9 layer.
Issues:
1. For the LPDDR4 section, the design of the 10-layer board is different from the 16-layer board (same impedance, different line width line spacing). And the customer is now going to use the "option B" approach. The customer would like to know if he can use the IBS model for simulation and fine-tuning, or is it necessary to refer to the design of the 10-layer board for layout? Would you like to offer some solution?
2: What is the internal DDR trace length of the TDA4VMid SOC?
Thanks!
Best Regards,
Cherry Zhou
