66AK2G12: In order to make 66AK communicate with another 66AK via PCIe (continue)

Please let me know if I asked something strange.

This problem is still unresolved.

Hello,

As mentioned in the previous thread, this isn't a typical use-case and as such isn't officially supported.

My suggestion for holding the EP in reset until the RC is ready might be accomplished by holding off on the EP initialization completely (TRM section 11.14.4.13.2.1). Once the RC is up and ready, you could configure the EP and then force a bus scan from the RC side.

Thank you for your response.

As you mentioned, I executed following Sequence (1)~(4) of TRM for EP by using Linux OS of SDK ( ver 06.03.00.106 processor-sdk-LINUX-RT-K2G).

11.14.4.13.2 PCIe as End Point
11.14.4.13.2.1 Initialization Sequence
Upon de-assertion of reset, the PCIe SS is configured as end point by chip-level setting in DEVCFG
register, see Section 5.1, Control Module (BOOT_CFG). Before a root complex is allowed to access the
configuration space of the end point, the following initialization sequence should be followed:
(1). Make sure PLL reference clock is running.
(2). Turn on the power domain and clock domain of PCIe module. See Section 5.2, Power Management,
for mare details.
(3). Set PCIE_DEV_TYPE to 0b0 in the device level register BOOTCFG_DEVCFG to operate the PCIe SS
in RC mode, see Section 5.1, Control Module (BOOT_CFG).
(4). Enable PLL using PCIE_PHY_PLL_CTRL register, see Section 11.14.4.8.1, Enabling the PLL, for
details.
(5). Wait until PLL is locked by sampling PLL_OK bit in the PCIE_PHY_PLL_CTRL register, see
Section 11.14.4.8.1, Enabling the PLL, for details.

However, 66AK as EP cannot be accomplished the Sequence of "(5) PLL is locked."

When we use 66AK as EP, PLL is not locked.

Reset, 100MHz reference clock and power-up Sequence is no prpblem,

because LTSSM is accomplished  "L0 (PCIe configurstion is done!)" when we use 66AK as RC.

-----question-----

What is condition that PLL of EP is locked ?

"Setting of PLL_ENABLE_VAL and PLL_ENABLE_OVL bits of PCIE_PHY_PLL_CTRL enables the internal PLL" is done, of course.

I think this question is common question.

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Thank you.