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Original question:

AM3352--DDR test

tCK(avg) test intems

user6150065
Prodigy 50 points

Dear

Hardware platform(AM3352ZCZA80+MT41K256M16TW-107).

Currently , we have another urgent topic about the DDR test item—Tck(avg)

This spec limitation is from 2.5ns~3.3ns, As you know,AM3352ZCZA80 support DDR3-800

So our clk is 400Mhz and the period is about 2.5ns, this test item is always fail.

My question is: Can we set the clk as less than 400Mhz(39?Mhz?)

  • 0
    TI__Guru* 87000 points

    You can drop to 392MHz, but many customers have not had issues running at 400MHz.  You may have an non-optimal DDR PLL setting.  Can you dump registers 0x44e00430-0x44e004a4 and post here?

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 50 points

    Hi James，

    We also don't meet issue with 400Mhz. but if we run 400Mhz. the tck(avg) test item is difficult to pass.

    The spec is 2.5ns~3.3ns，there is little margin.

    Anyway, I provide you the registers.

    Thanks.

  • 0 in reply to user6150065
    Prodigy 50 points

    Hi  sir

    Could you help to check this info asap?

    Thanks.

  • 0 in reply to JJD
    TI__Expert 5176 points

    Hi James,

    We are thinking about 2 methods to solve this issue, there are some questions on the tools, could you help?

    1) Set the clk as 392 MHz, but the DDR memory working freq in DDR memory frequency item can not be changed, just double confirm that it can still set this as 400MHz, and change the DDR PLL setting in the code directly.right?

    2)based on the DDR memory vendor suggestion, we set CL=7 CWL=6, but EMIF tools can not set this configuration, could you help check the next step?

  • +1 in reply to Thomas Yang55737
    TI__Guru* 87000 points

    It looks like the PLL settings are optimal based on a 24MHz system input clock

    The settings should be CL=6, CWL=5.  The one you have highlighted is to operate faster than 400MHz (it shows <2.5ns). 

    The  tCK(avg) measurement should be over a period of time and an average taken.  There may be times the tCK is below 2.5ns, but then other times it will be slower, and thus average out to 2.5ns

    Regards,

    James

  • +1 in reply to JJD
    Prodigy 50 points

    HI James

    We have adjust the DDR CLK to 392Mhz via PLL register.

    And the tCK(avg）is about 2.547ns and pass the test.

    We also do DDR stress test for a few days with 392Mhz and the result is pass.

    If you approve this status. we will launch 392Mhz in the future product.

    Is it ok ?

    Thanks.

  • +1 in reply to user6150065
    TI__Guru* 87000 points

    Yes, should be ok.

    James