This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi team,
The A72 runs Linux, requests a section of shared memory to write to the specified data, and sends the address and length to the R-core via the IPC. The R core receives the address by synchronizing cache with the CacheP_Inv(addr,len) function.
And the above method synchronizes data is working for MCU2_0 and mcu2_1, but is not good for MCU1_0. A core applied for memory using mmap(NULL, size, PROT_read | PROT_write | O_sync , map_shared, FD, 0).
So the customer would like to know is there any way to help resolve it? Could you help check this case? Thanks.
Best Regards,
Cherry
Hi Cherry,
This is a known issue in current SDK. There have been similar threads created previously.
regards
Suman
Hello Suman,
Thanks for your support here!
But why is IPC communication ok for 1-0? And the corresponding Resource Table update to the Resource Table is also use the function CacheP_Inv(addr,len) .
uint8_t Ipc_isRemoteReady(uint16_t procId) { uint8_t retVal = TRUE; Ipc_ResourceTable *rsc = NULL; if(TRUE == Virtio_isRemoteLinux(procId)) { rsc = (Ipc_ResourceTable*)rscTable; CacheP_Inv(rsc, sizeof(Ipc_ResourceTable)); if(rsc->rpmsg_vdev.status != 0x7U) { retVal = FALSE; } } return retVal; }
Thanks and regards,
Cherry
Hi Cherry,
Please see the discussion in similar previous thread and the published external JIRA https://sir.ext.ti.com/jira/browse/EXT_EP-10522.
The MCU1_0 is special, it is booted very differently from the other Main R5F Cores. MCU1_0 is special, it is a boot processor, and also provides a central device management functionality.
regards
Suman