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Original question:

RTOS/AM5728: How to reduce the delay from PC(RootComple) to negate INTA for PCI Express of AM5728

AM5728: PCIE Deassert INT function of sitara

matusan
Guru 10235 points
Part Number: AM5728

Hello, TI Experts,

 

Our customer sent us additional questions about from the below E2E thread.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/789337/rtos-am5728-how-to-reduce-the-delay-from-pc-rootcomple-to-negate-inta-for-pci-express-of-am5728

 

They designed their product which is connected to Windows-PC via PCIE-slot PCIE by using AM572x as EP(Endpoint).

 

And Now, they plan to select processor for next product.

At that time they needed to realize Deassert INT in PCIE-SS on AM572x by using FPGA logic like attached pdf.

 

They expect to use below function including removing this FPGA logic for next product.

https://docs.broadcom.com/doc/pex8311-detailed-technical-spec-data_Book-V1Dec2009

  - Deassert INTA by pin ( LINTi#-pin in page 56)

  - DMA Scatter/Gather Mode (1.2.2.2.2   DMA Scatter/Gather Mode in page37)

 

QUESTION:

   - Are there any sitara device have same function like above?

   - Or are there any sitara device which has any proper register for "deassert INTA" ?

 

Best regards,

2248.pcie.pdf

  • 0
    Guru 10235 points

    Hi,

     

    Thank you for your help.

    Now, Our customer is waiting for the answer.

     

    I would appreciate if you tell us about the progress on this.

     

    Best regards,

  • 0 in reply to matusan
    Mastermind 6300 points

    Hi,

    I am a colleague of matusan. Sorry for rush you. Is there any update? The customer is looking for an answer, so it would be helpful if you could tell us the status. If you have difficulty answering the part about this topic, or if you can answer offline, please let us know which one.

    Best regards,
    O.H