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Original question:

TDA4VM: Our own designed TDA4 board can not boot when Display Port 0(DP0) connect to a display

TDA4VM: TDA4VM

CHETAN BODAR
Prodigy 70 points
Part Number: TDA4VM
Other Parts Discussed in Thread: TIDEP-01020

Dear TI Technical Support  Team,

TDA4VM: Our own designed TDA4 board cannot boot when Display Port 0(DP0) connect to a display

As compare to evaluation kit, Only change in our design is ; we have directly connected V3V3_DP0 to V3.3 supply i.e. we have removed LDO.

Please find below schematic.

But I am seeing other forum of TI , similar issues reported by other designer even they have followed same design as evaluation kit.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/956479/tda4vm-our-own-designed-tda4-board-can-not-boot-when-display-port-0-dp0-connect-to-a-display 

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/980716/tda4vm-our-customized-tda4-board-cannot-be-started-when-dp0-is-connected-to-the-display

Please provide your feedback for the same.

Thanks

Chetan Bodar

  • 0
    Intellectual 256 points

    We meet the same issue in the first time, too,

    we isolated the HPD signal and SOC with a  MOSFET “Isolator”, you can also find this circuit in TIDEP-01020.

    I don't know what causes the failure boot without isolator, but it really works, 

    I also want to know the exact mechanism about it. 

  • 0 in reply to Yantao Dong
    TI__Guru 53695 points

    Both E2E link suggest the issue is the customer design did not properly implement the DisplayPort power circuit.  It appears power to the panel (from the customer design) is remaining on (or on by default).  Compare that with TI’s EVM – the power to the panel is disabled by default – and must be enabled by software after boot.  This issue is if the monitor is powered, it can drive the monitor detect signal (HPD) back into the processor prior to the processor being powered.  This is a violation and can cause leakage int the device.  The can cause unpredictable behavior in the processor.  Also – the PMIC circuit have safety features and can detect if the leakage gets beyond a certain voltage – and cause the system to not even power up.

     

    The fix is to disable power to the monitor until the system is booted.  The E2E suggest they are isolating the HPD signal from the processor and are having success.  This may work also (assuming there are no other leakage paths) – but I think preferred fix would be to power display panel at proper time.

  • 0 in reply to Robert Eschler
    Intellectual 256 points

    Thanks,  Bob

    Yes, power up sequence between the EVM（or TDA4 product）and DP causes voltage leakage to SOC， and safety feature detects it and takes the proper operation to stop the boot.

    Fortunately, we don't use DP(or) HDMI for mass production in automobile area,  they have too many bugs.  FPD-LINKIII or GMSL should be the better choice.   

      

  • 0
    Prodigy 70 points

    Dear Team,

    Thanks for feedback , We will try to disable Power monitor during boot time in SW and keep you posted if problem is solved or any further support required.

    Thanks,

    Chetan Bodar