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OMAP-L138: Inquiry about LPDDR Initialization

Part Number: OMAP-L138

Hi Team,

Our customer develop their system board with OMAP-L138, due to LPDDR shortage issue, customer replaced LPDDR with other one. However, it seems customer encountered the issue. Although customer investigating this issue, they noticed that OMAP-L138 does not wait for 200 usec with NOP. According to JEDEC standard spec, there is the description which is “Wait at least 200 µs with NOP or DESELECT on command bus” (OMAP-L138_LPDDR_Initialization.pdf).

Customer checked OMAP-L138’s TRM (15.2.13.1 Initializing Following Device Power Up or Reset ), however, customer was not able to understand how to configure the registers actually.

Can I have your Expert’s advice/comments on this, please?

it is really appreciated your quick reply because customer’s production already is delayed.

Best regards,

Miyazaki

  • Hi Experts,

    Customer measured AC timing with their system boards. I attached it ( Actual_Measurement_Result.pdf ).

    it is really appreciated your quick reply.

    Best regards.

    Miyazaki

  • This has been assigned to a hardware expert, however please see that they are not susceptible to 

    2.1.5 DDR2/mDDR Controller: mDDR Usage Note in the errata

    https://www.ti.com/lit/er/sprz301m/sprz301m.pdf

  • Hi Mukul,

    Thank you for your advice.

    I see... Should I ask customer what kind of LPDDR customer are using? I mean, should I clarify LPDDR device name?

    Best regards,

    Miyazaki

  • Ensure they are following the initialization steps in the TRM, section 15.2.13.1.  Also ensure they are using https://www.ti.com/lit/pdf/spracq4 to configure the DDR controller and PHY

    Regards,

    James

  • Hello James, Mukul,

    I shared your comments ith customer. I'd like to wait for your feedback.

    Best regards,

    Miyazaki

  • Hi James,

    I discussed this issue with customer, and I gathered this issue’s background with calling.

    Previously, customer was using LPDDR which is supporting Status Read Register (SRR). However, due to device shortage issue, customer replaced it with other LPDDR device. This LPDDR device does not support SRR, therefore, there is not possibility that this issue is related to  “2.1.5 DDR2/mDDR Controller: mDDR Usage Note” in errata list. First of all, although customer was asking DDR device maker, this maker is asking customer if customer’s system is obeying powerup sequence like JESD209B specification, correctly. Since customer noticed there was violation that is OMAP-L138 does not wait for at least 200usec, they are asking how to control this 200usec.

    Customer already read “15.2.13 Auto-Initialization Sequence”, and they understood OMAP’s mDDR initialization sequence is compliant with the JESD209 specification. Certainly, customer is not sure if this issue is related to this 200usec-waiting at this time , however, customer is not able to mention the Memory-vendor that customer is controlling it correctly.

    And then, customer tried to understand TI’s spreadsheet, they are not sure if customer is able to control this waiting-time with OMAP-L138’s registers.

    Therefore, customer is asking how to control this waiting-period at first. Can we have your expert’s advice/comments on this, please?

    If you have any advice what customer should do analysis, would you share your advice, please?

    When this issue occurred, it seems device-reset was repeated.

    Best regards,

    Miyazaki

  • Hello James-san,

    Can I have your further advice for this issue, please?

    Best regards,

    Miyazaki

  • Hello James-san,

    If customer should do analysis of other points, could you share your further advice, please?

    I'll try to request customer to do that.

    Best regards,

    Miyazaki

  • Hello James-san,

    I’m Miyazaki-san’s customer, Furuya.

    As Miyazaki-san reported, we are encountering LPDDR issue after replacing LPDDR with other one now.
    We already referred “15.2.13 Auto-Initialization Sequence” in TRM and engineers in Japan and the US each confirmed that ensured our firmware was following the initialization step. 
    In addition, we re-checked EMIF spreadsheet and confirmed there were not any miss.
    I mean, I have verified that the mDDR configuration in the our bootloader matches the procedure specified in 15.2.13.1 exactly.
    But, we are not sure the method how to control this 200usec.
    We’d like to request DDR manufacturer to consult this issue, however, we need to fix this JESD209B initialization violation of the before that.

    Can we have TI’s advice, as soon as possible, please?

    Mass production is stopping now. Your quick reply will be really appreciated.

    Best regards,

    Furuya