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DRA821U: SERDES REFCLOCK (PCIe) Reference Clock Input Characteristics

Stuart Baker
Genius 10690 points
Part Number: DRA821U
Other Parts Discussed in Thread: DRA821,

This is related to a previous question I have asked here:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1073497/dra821u-serdes0_refclk-termination-when-used-as-input

Customer is asking:

Can you clarify what the max single ended voltage threshold spec actually means? Our driver has a max single ended voltage output of 850mV. Can you also provide details on what the DRA821 internal termination looks like?

They are referring to the 400mV Single Ended Voltage Threshold in our datasheet.

Thanks,

Stuart

  • 0
    TI__Genius 17116 points

    This voltage limit in the datasheet corresponds to the parameter "VMAX, Absolute Max input voltage" from the PCIe specification. The voltage limit only applies when the internal 50-ohm termination on each leg is turned on. An 850mV driver will violate this limit, therefore the internal termination resistors should not be used. The termination should instead be populated on the PCB (or HCSL drivers), or included in the driver itself (for LP-HSCL drivers).

  • 0
    Prodigy 50 points

    What termination is recommended with PI6CG18801 LP-HCSL driver?

  • 0 in reply to Jonathan West
    TI__Genius 17116 points

    PI6CG18801 has on-chip termination, therefore:

    - The DRA821U internal 50ohm termiantion should be disabled

    - 50ohm termination to GND should NOT be placed on the PCB

    I also do not see any recommendation for external series damping termination mentioned in the PI6CG18801 datasheet.

    In summary, the PI6CG18801 outputs should be directly connected to the DRA821U inputs.

  • 0 in reply to B.C.
    TI__Genius 10690 points

    BC,

    What about series DC blocking capacitors, as mentioned in the referenced E2E thread above? Should these still be used?

    Thanks,

    Stuart

  • 0 in reply to Stuart Baker
    TI__Genius 17116 points

    No, neither HSCL nor LP-HSCL use DC blocking caps. Those would only be necessary if rebiasing the common mode, for example when trying to interface an LVDS output with an HSCL-compliant input.

  • 0 in reply to B.C.
    TI__Genius 10690 points

    BC,

    This has been very helpful. We one last set of related questions regarding startup state and power rail sequencing.

    According to the datasheet, the SERDES REFCLK pins are powered from the VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, and VDDA_0P8_SERDES0_C rails. This design uses the Combined MCU and Main Domains Power-Up Sequencing. Must some or all of these rails be powered up before applying a clock to the SERDES REFCLK inputs?

    Further, what is the default startup state of the SERDES REFCLK? From the TRM, it looks like they are setup as inputs with on-chip termination enabled (SERDES_RST.REFCLK_TERM_DIS). I'm not sure which register/bit sets the SERDES REFCLK as an input or output.

    Thanks,

    Stuart

  • +1 in reply to Stuart Baker
    TI__Genius 17116 points

    All of the *SERDES* power rails must be powered up before applying a clock to the SERDES REFCLK inputs.

    In PCIe Boot Mode, BOOTMODE pin 4 selects between input and output REFCLK modes, and the internal termination is enabled in Silicon Revision 1.0. However, the internal termination will changed to being disabled in PCIe Boot Mode on future Silicon Revisions. For Silicon Revision 1.0, software should manually disable the internal termination when using an external REFCLK input.

  • 0 in reply to B.C.
    TI__Genius 10690 points

    BC,

    This has been very helpful, I think we have all the information we need.

    Thanks,

    Stuart