TDA4VM: How to disable the LFSR DQ training feature of DDR?

Yao Zhang

Part Number: TDA4VM

Hi,

Sometimes our board with TDA4VM SoC can't work on the 2133MHz DDR.

We need to locate this problem and it's need to disable the LFSR DQ training feature.

Please provide the method to disable the LFSR DQ training feature, thanks.

0 Kevin S over 3 years ago

Hi,

Please see the post below. The parameter PHY_WDQLVL_PATT_* contains the patterns used during write data training. Bit 0 corresponds to LFSR.

Regards,
Kevin

0 Yao Zhang over 3 years ago in reply to Kevin S

hi expert

Modify as shown in the link TDA4VM Running ok

when i read the TRM and found LFSR training pattern can be use work around and ti are continue optimize setting

and ti do not suggerst customer disable TDA4VM periodic writing DQ training ,it just for debug and not used for mass product

my question is

What will be the impact of closing LFSR DQ

If it is a workaround , when will the mass production solution be resolved

Regards

yao

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