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SK-AM64: Question about CPSW0 CPTS_CLKSEL

Yun Park
Prodigy 120 points
Part Number: SK-AM64


Hello,

I’m working on the CPSW Ethernet driver on AM642 (SDK 8) and have some questions:

  1. I want to set CTRLMMR_CPTS_CLKSEL register to 0x7 (MAIN_SYSCLK0), but when I write to this register, its value is not changed and keeps 0. As described in the TRM, I cleaned the CPTS_EN bit to 0. before write this. Then is there any other restriction in writing to this register? CTRLMMR_CPSW_CLKSEL is set to 0x7, same as Linux.
  2. AM64X TRM Fig 12-344 CPSW0 Integration shows that CTPS_RFT_CLK is selected by CTRLMMR_CPTS_CLKSEL register, but Fig 12-353 CPSW0 CPTS Integration shows that it's selected by CTRLMMR_CPSW_CLKSEL register. Which one is correct?

 Thanks,

  • 0
    Prodigy 120 points

    Hello, is there any update for this question?

    Now I have some confusion about the CPTS reference clock (CPTS_RCLK) selector.

    In the TRM, I could see there are some different registers to set the CPTS RCLK:

    - CTRLMMR_PCIE0_CLKSEL[2-0] CPTS_CLKSEL register field

    - CTRLMMR_CPTS_CLKSEL register's CPTS_CLKSEL field

    - CPSW_CPTS_RFTCLK_SEL_REG (0x0803d008h),

    - CPTS_RFTCLK_SEL_REG (0x39000008h)

    What's the relationship among all these registers and what I actually need to use to set the CPTS_RCLK?

  • +1 in reply to Yun Park
    TI__Mastermind 27050 points

    Yun,

    There is 3 separate CPTS modules in AM64x. One in CPSW subsystem (IEEE1588), one in PCIe (for use with PCIe PTM), and another at the main SoC level. All these can be independently configured, and they can be tied to each other with the genf events to create tuples of when this CPTS was X, the other one was Y.

    Yun Park said:
    I want to set CTRLMMR_CPTS_CLKSEL register to 0x7 (MAIN_SYSCLK0), but when I write to this register, its value is not changed and keeps 0. As described in the TRM, I cleaned the CPTS_EN bit to 0. before write this. Then is there any other restriction in writing to this register? CTRLMMR_CPSW_CLKSEL is set to 0x7, same as Linux.

    Did you follow the unlock procedure (5.1.1.3.1.2 Kick Protection Registers) to enable modifying the CTRL MMRs? In case you didn't here is a sequence I use from Linux command line to unlock them all:

    #unlock CTRL MMR kick register sequence
devmem2 0x43001008 w 0x68EF3490
devmem2 0x4300100C w 0xD172BC5A
devmem2 0x43005008 w 0x68EF3490
devmem2 0x4300500C w 0xD172BC5A
devmem2 0x43009008 w 0x68EF3490
devmem2 0x4300900C w 0xD172BC5A
devmem2 0x4300D008 w 0x68EF3490
devmem2 0x4300D00C w 0xD172BC5A
# TRM does not have lock4 register intentional omit as reserved
devmem2 0x43015008 w 0x68EF3490
devmem2 0x4301500C w 0xD172BC5A
devmem2 0x43019008 w 0x68EF3490
devmem2 0x4301900C w 0xD172BC5A
devmem2 0x04501008 w 0x68EF3490
devmem2 0x0450100C w 0xD172BC5A
devmem2 0x04505008 w 0x68EF3490
devmem2 0x0450500C w 0xD172BC5A
devmem2 0x04509008 w 0x68EF3490
devmem2 0x0450900C w 0xD172BC5A
devmem2 0x0450D008 w 0x68EF3490
devmem2 0x0450D00C w 0xD172BC5A
# TRM does not have lock4, lock5 intentional omit as reserved
devmem2 0x04519008 w 0x68EF3490
devmem2 0x0451900C w 0xD172BC5A

    Yun Park said:
    AM64X TRM Fig 12-344 CPSW0 Integration shows that CTPS_RFT_CLK is selected by CTRLMMR_CPTS_CLKSEL register, but Fig 12-353 CPSW0 CPTS Integration shows that it's selected by CTRLMMR_CPSW_CLKSEL register. Which one is correct

    I believe the CTRLMMR_CPSW_CLKSEL is for the CPTS in the CPSW, and the CTRLMMR_CPTS_CLKSEL is for the SoC level CPTS. The one in PCIE is called CTRLMMR_PCIE0_CLKSEL . The figure 12-344 is the SoC level diagram, the CPTS inside the CPSW block of that diagram is then shown in 12-353.

      Pekka

  • 0 in reply to Pekka Varis
    Prodigy 120 points

    Thanks Pekka,

    Now I could modify CTRLMMR_CPTS_CLKSEL by unlocking the kick protection registers lock2_kick0 and kick1 (partition 2, offset range 0x8000 to 0x9fff).

    So, per Fig 12-344 and 353, to configure CPTS_RCLK for CPSW, need to configure both CTRLMMR_CPTS_CLKSEL and CTRLMMR_CPSW_CLKSEL, is it right?

  • +1 in reply to Yun Park
    TI__Mastermind 27050 points

    Great. It looks like the Figure 12-344 is actually incorrect. The three CPTS modules in AM64x are independent with regard to the clock source like I described above. But the diagram 12-344 is not correct, for Ethernet /CPSW you can just use CTRLMMR_CPSW_CLKSEL as shown in Figure 12-353, no need to configure CTRLMMR_CPTS_CLKSEL. The figure 12-344 should also show CTRLMMR_CPSW_CLKSEL. The SoC level, or main CPTS, configured with CTRLMMR_CPTS_CLKSEL is separate.

    I'll file a documentation bug, in the meanwhile the whole time sync hierarchy is not well documented in the TRM yet, this post has a good description.

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1061474/faq-am64x-what-is-the-time-sync-router-for-how-do-i-use-it

      Pekka