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DM37xx with nor flash of Spansion S29NS512P

Oscar Gomez Fuente
Expert 2066 points
Other Parts Discussed in Thread: DM3730

Hi, I am interesting in develop a platform with the DM37xx microprocessor, a POP memory with [4Gb Nand flash + 2Gb LPDDR] of micron: MICMT29C4G48MAZAPAKQ-5 IT and a nor flash of Spansion: S29NS512P (no PoP, externally connected). 

I'd like boot from nor flash (I have aviable 512 Mbits for u-boot, kernel and root file system) and use nand flash for log files and store images. I'd have to connect CS0 to Nor flash and CS1 to nand flash. Is that correct?

Can I use NOR flash for read and wirte? I found an application note of spansion1263.SpansionNOR-AM35x.pdf, where describes how use a S29NS512R nor flash, but only for read, for Sitara processors, but the GPMC module as identical. The S29NS512P[90 nm technology] and S29NS512R[65 nm technology] are identical nor flash but with different manufacturing technology.

Thank you very much.

 

 

 

  • 0
    TI__Expert 6735 points

    Oscar:

    Here is a similar thread that may be helpful:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/537/p/99052/346594.aspx#346594

    AM37x has these characteristics for memory boot from XIP memory like NOR flash.

    Looks like you must boot NOR from GPMC CS0. 

    26.4.7.3 XIP Memory

    The ROM code can boot directly from XIP booting devices, such as NOR flash memories, that have the

    following characteristics:

    • The GPMC is the communication interface.

    • Memories up to 2 Gb (256MB) can be connected.

    • x16 data bus width only

    • Asynchronous protocol and address/data multiplexed mode

    • The GPMC clock is 48 MHz.

    • The booting device is connected to CS0 mapped to address 0x0800 0000.

    • The wait pin signal gpmc_wait0 is monitored according to the sys_boot configuration pins.

    Regards,

    Michael T

  • 0 in reply to Michael T
    Expert 2066 points

    Hi, Michael.

    If I use a PoP package for Nand Flash + LPDDR (MICMT29C4G48MAZAPAKQ-5 IT), using the top ball of DM3730, and I use a nor flash connected to gpmc_cs0, using the bottom balls of DM3730, nand flash and nor flash will be connected to the same chip select, gpmc_cs0.  Right?

    Is it possible to use a nand flash (PoP, use top balls) and a nor flash (MCP, use bottom balls) at once?

    Can I change boot from nand flash to nor flash? With nor flash I have no problems, with two resistors 0R could change the chip select gpmc_cs0 to gpmc_cs1, but with nand flash, Is there possibility to change the chip select gmpc_cso to gpmc_cs1, at the top balls,  changing a configuration register?

    Thank you very much.

  • 0 in reply to Oscar Gomez Fuente
    TI__Expert 6735 points

    Oscar:

    gpmc_cs0 at top or bottom is the same signal.

    Boot media must be on CS0.

    You cannot redefine the gpmc_ncs0 and gpmc_ncs1 pins they are on separate balls (each at top and bottom) and

    they are both available after reset in mux mode 0.   You program the gpmc config registers to set the base address

    and size for each chip select.   NOR is memory mapped and XIP (execute in place).  NAND is accessed via mtd/nand driver.

    Regards,

    Michael T

    PS: Please mark this post as answered via the Verify Answer button below if you think it answers your question.  Thanks!