TDA4VM: Initlialzing DDR ... hang when SBL+OSPI Flash boot up

Sancho Huang

Part Number: TDA4VM

Hi TI,

We use DDR(MT53D1024M32D4DS-053:B(4GB,4266MHz)) in our custom board and config the new DDR parameter(k3-j721e-ddr-evm-lp4-3200.dtsi for SPL, board_ddrRegInit.h for SBL) according spracu8.pdf
It can boot in my custom board via SPL+SD bootup, but it will hang at "Initlialzing DDR ..." when use SBL+OSPI Flash boot up.
I try to add some debug message in board_ddr.c and lpddr4.c when initialize DDR and found it hang in LPDDR4_StartSequenceController() function.

This is my diff about lpddr4.c file

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diff --git a/packages/ti/csl/src/ip/lpddr/V0/priv/lpddr4.c b/packages/ti/csl/src/ip/lpddr/V0/priv/lpddr4.c
index 3b7f228..0924a9b 100644
--- a/packages/ti/csl/src/ip/lpddr/V0/priv/lpddr4.c
+++ b/packages/ti/csl/src/ip/lpddr/V0/priv/lpddr4.c
@@ -47,6 +47,9 @@
 #include "lpddr4_ctl_regs_rw_masks.h"
 #endif
 
+#include <ti/drv/uart/UART_stdio.h>
+#include <ti/drv/uart/UART.h>
+
 #ifndef LPDDR4_CUSTOM_TIMEOUT_DELAY
 #define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U
 #endif
@@ -248,6 +251,7 @@ uint32_t LPDDR4_Start(const LPDDR4_PrivateData* pD)
     uint32_t result = 0U;
     uint32_t regVal = 0U;
 
+    UART_printf("[xxx] in LPDDR4_Start start\n");
     result = LPDDR4_StartSF(pD);
     if (result == (uint32_t)CDN_EOK) {
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

diff --git a/packages/ti/csl/src/ip/lpddr/V0/priv/lpddr4.c b/packages/ti/csl/src/ip/lpddr/V0/priv/lpddr4.c
index 3b7f228..0924a9b 100644
--- a/packages/ti/csl/src/ip/lpddr/V0/priv/lpddr4.c
+++ b/packages/ti/csl/src/ip/lpddr/V0/priv/lpddr4.c
@@ -47,6 +47,9 @@
 #include "lpddr4_ctl_regs_rw_masks.h"
 #endif
 
+#include <ti/drv/uart/UART_stdio.h>
+#include <ti/drv/uart/UART.h>
+
 #ifndef LPDDR4_CUSTOM_TIMEOUT_DELAY
 #define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U
 #endif
@@ -248,6 +251,7 @@ uint32_t LPDDR4_Start(const LPDDR4_PrivateData* pD)
     uint32_t result = 0U;
     uint32_t regVal = 0U;
 
+    UART_printf("[xxx] in LPDDR4_Start start\n");
     result = LPDDR4_StartSF(pD);
     if (result == (uint32_t)CDN_EOK) {
         LPDDR4_CtlRegs* ctlRegBase = (LPDDR4_CtlRegs*)pD->ctlBase;
@@ -258,8 +262,11 @@ uint32_t LPDDR4_Start(const LPDDR4_PrivateData* pD)
         CPS_REG_WRITE((&(ctlRegBase->LPDDR4__PI_INIT_LVL_EN__REG)), regVal);
 
         /* Start PI init sequence. */
+        UART_printf("[xxx] LPDDR4_StartSequenceController start\n");
         result = LPDDR4_StartSequenceController(pD);
+        UART_printf("[xxx] LPDDR4_StartSequenceController end\n");
     }
+    UART_printf("[xxx] in LPDDR4_Start end\n");
     return result;
 }

The MCU uart log output is:

I upload the DDR config file board_ddrRegInit, I hope it will be helpful to investigate the problem.

7571.board_ddrRegInit.zip

SDK Version is 07.03.

BR.

Sancho

over 3 years ago

0 Sancho Huang over 3 years ago

Prodigy 215 points

Hi TI,

The DDR part number I said before was wrong, the correct one is MT53E1G32D2FW-046 AUT:A(4GB,4266MHz).

BR.

Sancho

0 Kevin S over 3 years ago

TI__Mastermind 35150 points

Hi,

You mentioned it works fine with SPL + SD card, and fails with SBL + OSPI.

Is "SPL" and "SBL" referring to two different source repositories?
Are there other differences outside of the boot medium (SD card vs, OSPI) when comparing the passing case vs. the failing case?

Can you add more print logs inside the startsequencecontroller function?

Thanks,
Kevin

0 Sancho Huang over 3 years ago in reply to Kevin S

Prodigy 215 points

Hi, Kevin

1. Yes, SPL build out from Linux SDK: ti-processor-sdk-linux-j7-evm-07_03_00_05/board-support/u-boot-2020.01+gitAUTOINC+2781231a33-g2781231a33
SBL build out from RTOS SDK: ti-processor-sdk-rtos-j721e-evm-07_03_00_07/pdk_jacinto_07_03_00_29/packages/ti/boot/sbl
2. I also try use SPL + OSPI, it boot successful in my custom board, so I think the difference is only SBL and SPL.
3. OK, I wil add more debug message in LPDDR4_StartSequenceController() function and feedback within a day.

BR.
Sancho

0 Juanli Zhang over 3 years ago in reply to Sancho Huang

Intellectual 360 points

Hello Team,

The DDR4 (MT53E1G32D2FW-046 AUT:A) schematic as attached.

Best Regards

Juanli Zhang

DDR SCH.pdf

0 Sancho Huang over 3 years ago in reply to Kevin S

Prodigy 215 points

Hi, Kevin

I found the code was stuck in check BOARD_DDR_FSP_CLKCHNG_REQ_ADDR value when initilize DDR.

The MCU uart log output is:

BR.
Sancho

0 Sancho Huang over 3 years ago in reply to Kevin S

Prodigy 215 points

There is a similar problem with TDA4VM: Stop at "Initlialzing DDR ..." using SBL when doing soft reset.

0 Kevin S over 3 years ago in reply to Sancho Huang

TI__Mastermind 35150 points

Hi,

Thanks for the additional information. Additionally, can you check the value of DDRSS_CTL_0 (address 0x02990000) just before the Board_DDRHWRegInit function? I'd like to confirm that the lowest bit = 0 and that no other code could have possibly already tried to initialize the DDRSS.

Thanks,
Kevin

0 Sancho Huang over 3 years ago in reply to Kevin S

Prodigy 215 points

Hi, Kevin

The value of DDRSS_CTL_0(address 0x02990000) register is 0x10460000 before Board_DDRHWRegInit() function.

BR.

Sancho

+1 Sancho Huang over 3 years ago in reply to Sancho Huang

Prodigy 215 points

Hi, Kevin

After change the DDR config(impedance parameters and refresh time), the problem is resolved.
Thank for you support.

BR.
Sancho

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TDA4VM: Initlialzing DDR ... hang when SBL+OSPI Flash boot up