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Original question:

TMS320C6678: Sending DMA "transfer completion" indication to FPGA on the same board.

TMS320C6678: Mapping of EDMA3CC sync event from Queue Manager via CIC

Islombek Karimov
Prodigy 80 points
Part Number: TMS320C6678

Hi!

I would like to configure an interrupt from Queue Manager which should be an input event to CIC which then would send an input sync event to EDMA3CC to start the EDMA3 channel transfer. 

Specifically, I would like to understand which queue event corresponds to which QM interrupt and how to relate that to CIC input events and EDMA3CC sync events? 

For example, I can see that QM Interrupt QM_INT_HIGH_16 is an input event #24 for CIC2 (according to Table 7-40 in SPRS691E). I can also see that CIC2's output can trigger an input sync event to EDMA3CC1 and EDMA3CC2. Which CIC2 output interrupt does QM_INT_HIGH_16 input event correspond to? Also, what is QM_INT_HIGH_16 and when does it occur? 

My ultimate goal is to trigger an EDMA3CC channel as soon as an Ethernet packet is received and queue has been pushed to by Queue Manager, i.e. exactly what is described in sprugr9h in chapter 2.3.3: "This is an application-selected queue that doesn’t necessarily have special hardware such as a que_pend signal, though for certain use-cases, the selected receive queue may also be a transmit queue for another PKTDMA, or a queue pend queue that triggers other functionality such as EDMA."

Thanks!

  • 0
    TI__Expert 4314 points

    Hi Islombek,

    1488.Configuring Interrupts K1.pdf All CIC interrupts can be configured and attached to the event.

    In the Document, The CIC interrupt attached with Hyperlink Event is used. It needs to be modified for EDMA3. Example code is provided on Page  4 and 5. 

    /*** --- INTC Initializations --- ***/

/* Note that hyplnk_EXAMPLE_COREPAC_VEC = 4, hyplnk_EXAMPLE_COREPAC_INT_INPUT = 0x15, */
/* CSL_INTC_CMD_EVTCLEAR = 3, CSL_INTC_CMD_EVTENABLE = 0 */

CSL_IntcParam vectId = hyplnk_EXAMPLE_COREPAC_VEC; 
Int16 eventId = hyplnk_EXAMPLE_COREPAC_INT_INPUT;
CSL_IntcGlobalEnableState   state;

/* INTC module initialization */
hyplnkExampleIntcContext.eventhandlerRecord = hyplnkExampleEvtHdlrRecord;
hyplnkExampleIntcContext.numEvtEntries      = 2;
CSL_intcInit(&hyplnkExampleIntcContext);  

/* Enable NMIs */
CSL_intcGlobalNmiEnable(); 

/* Enable global interrupts */
CSL_intcGlobalEnable(&state);

hyplnkExampleIntcHnd = CSL_intcOpen (&hyplnkExampleIntcObj, eventId, &vectId, NULL);
hyplnkExampleEvtHdlrRecord[0].handler = hyplnkExampleIsr;
hyplnkExampleEvtHdlrRecord[0].arg = (void *)eventId;
CSL_intcPlugEventHandler(hyplnkExampleIntcHnd, hyplnkExampleEvtHdlrRecord);

/* Clear the event in case it is pending */
CSL_intcHwControl(hyplnkExampleIntcHnd, CSL_INTC_CMD_EVTCLEAR, NULL);

/* Enable event */
CSL_intcHwControl(hyplnkExampleIntcHnd, CSL_INTC_CMD_EVTENABLE, NULL);

/*** --- CIC Initializations --- ***/

CSL_CPINTC_Handle hnd;
hnd = CSL_CPINTC_open (0);
  
/* Disable all host interrupts. */
CSL_CPINTC_disableAllHostInterrupt(hnd);
    
/* Configure no nesting support in the CPINTC Module */
CSL_CPINTC_setNestingMode (hnd, CPINTC_NO_NESTING);

/* Clear Hyperlink system interrupt number 111 */
/* We get the interrupt number from Table 7-39 in the 6678 */
/* data manual at http://www.ti.com/lit/ds/sprs691c/sprs691c.pdf */
CSL_CPINTC_clearSysInterrupt (hnd, CSL_INTC0_VUSR_INT_O);

/* Enable Hyperlink system interrupt number 111 on CIC0 */
CSL_CPINTC_enableSysInterrupt (hnd, CSL_INTC0_VUSR_INT_O);

/* Map System Interrupt to Channel. */
/* Note that hyplnk_EXAMPLE_INTC_OUTPUT = 32 + (11 * CoreNumber) = 43 for Core0*/
CSL_CPINTC_mapSystemIntrToChannel (hnd, CSL_INTC0_VUSR_INT_O, hyplnk_EXAMPLE_INTC_OUTPUT);  

/* Enable the Host Interrupt */
CSL_CPINTC_enableHostInterrupt (hnd, hyplnk_EXAMPLE_INTC_OUTPUT);

CSL_CPINTC_enableAllHostInterrupt(hnd);

    For completion detection, 

    EDMA3_DRV_Result EDMA3_DRV_registerTccCb	(	EDMA3_DRV_Handle 	hEdma,
const uint32_t 	channelId,
EDMA3_RM_TccCallback 	tccCb,
void * 	cbData	 
)

    This API generates the callback to the Interrupt. In our case, It is the CIC interrupt.

    Thanks,

    Rajarajan U

  • 0 in reply to Rajarajan Uthayakumar
    Prodigy 80 points

    Thanks for the response. 

    Could you tell me what are the QM_INT_HIGH_16 to QM_INT_HIGH_31 interrupts and when do they occur? The description just says "QM interrupt" but it doesn't tell anything useful. 

    I want an interrupt from Queue Manager immediately when my receive queue is filled with a packet / Ethernet frame. 

  • 0 in reply to Islombek Karimov
    TI__Expert 4314 points

    Hi Islombek,

    Islombek Karimov said:
    Could you tell me what are the QM_INT_HIGH_16 to QM_INT_HIGH_31 interrupts and when do they occur? The description just says "QM interrupt" but it doesn't tell anything useful.

    QM_INT_HIGH_16 to QM_INT_HIGH_31 is the Interrupt Input events, which will trigger the Interrupt. 

    In the below example, the Event is mapped to CIC0 Interrupt.

    /*** --- INTC Initializations --- ***/

/* Note that hyplnk_EXAMPLE_COREPAC_VEC = 4, hyplnk_EXAMPLE_COREPAC_INT_INPUT = 0x15, */
/* CSL_INTC_CMD_EVTCLEAR = 3, CSL_INTC_CMD_EVTENABLE = 0 */

CSL_IntcParam vectId = hyplnk_EXAMPLE_COREPAC_VEC; 
Int16 eventId = hyplnk_EXAMPLE_COREPAC_INT_INPUT;
CSL_IntcGlobalEnableState   state;

/* INTC module initialization */
hyplnkExampleIntcContext.eventhandlerRecord = hyplnkExampleEvtHdlrRecord;
hyplnkExampleIntcContext.numEvtEntries      = 2;
CSL_intcInit(&hyplnkExampleIntcContext);  

/* Enable NMIs */
CSL_intcGlobalNmiEnable(); 

/* Enable global interrupts */
CSL_intcGlobalEnable(&state);

hyplnkExampleIntcHnd = CSL_intcOpen (&hyplnkExampleIntcObj, eventId, &vectId, NULL);
hyplnkExampleEvtHdlrRecord[0].handler = hyplnkExampleIsr;
hyplnkExampleEvtHdlrRecord[0].arg = (void *)eventId;
CSL_intcPlugEventHandler(hyplnkExampleIntcHnd, hyplnkExampleEvtHdlrRecord);

/* Clear the event in case it is pending */
CSL_intcHwControl(hyplnkExampleIntcHnd, CSL_INTC_CMD_EVTCLEAR, NULL);

/* Enable event */
CSL_intcHwControl(hyplnkExampleIntcHnd, CSL_INTC_CMD_EVTENABLE, NULL);

/*** --- CIC Initializations --- ***/

CSL_CPINTC_Handle hnd;
hnd = CSL_CPINTC_open (0);
  
/* Disable all host interrupts. */
CSL_CPINTC_disableAllHostInterrupt(hnd);
    
/* Configure no nesting support in the CPINTC Module */
CSL_CPINTC_setNestingMode (hnd, CPINTC_NO_NESTING);

/* Clear Hyperlink system interrupt number 111 */
/* We get the interrupt number from Table 7-39 in the 6678 */
/* data manual at http://www.ti.com/lit/ds/sprs691c/sprs691c.pdf */
CSL_CPINTC_clearSysInterrupt (hnd, CSL_INTC0_VUSR_INT_O);

/* Enable Hyperlink system interrupt number 111 on CIC0 */
CSL_CPINTC_enableSysInterrupt (hnd, CSL_INTC0_VUSR_INT_O);

/* Map System Interrupt to Channel. */
/* Note that hyplnk_EXAMPLE_INTC_OUTPUT = 32 + (11 * CoreNumber) = 43 for Core0*/
CSL_CPINTC_mapSystemIntrToChannel (hnd, CSL_INTC0_VUSR_INT_O, hyplnk_EXAMPLE_INTC_OUTPUT);  

/* Enable the Host Interrupt */
CSL_CPINTC_enableHostInterrupt (hnd, hyplnk_EXAMPLE_INTC_OUTPUT);

CSL_CPINTC_enableAllHostInterrupt(hnd);

    Variable "eventId" stores the event ID that needs to be mapped to Interrupt. And, "hyplnkExampleIntcHnd = CSL_intcOpen (&hyplnkExampleIntcObj, eventId, &vectId, NULL);". This steps combines the EventId wih Interrupt CIC0.

    Also, refer to the PA example for the C6678 generated from RTOS -SDK Queue management. 

    Thanks,

    Rajarajan U