TMS320C6678: Sending DMA "transfer completion" indication to FPGA on the same board.

Hello!

I see at least 2 possible scenarios to complete your goal:

1. Setup chained transfer, which effectively would write to FPGA over SRIO to make completion notification.
2. Setup completion ISR and do that using processor.

If option 1 suffice, there is no reason for option 2.

Next, I am not fluent in SRIO, just guessing. Sometimes in PCIe there is an vendor extension, which makes it possible to signal MSI towards endpoint. I would look for such a feature in SRIO as well.

Thank you for the response! 

The DMA that's currently transferring data (Ethernet) from DSP's network coprocessor to the buffer is Packet DMA inside Queue Manager. 
If I want to chain another DMA configuration to write the indication, is this feasible with Packet DMA and another DMA on this DSP (EDMA, for instance)? How would I do that?

Victor Kazmirenko said:

SRIO

Hello,

Queue Manager is still terra incognita to me, I don't feel myself fluent enough to give recommendations.

Nevertheless, in your shoes I would look for some event to tie QM and EDMA. In C6678 datasheet, clause 7.10 lists interrupt sources. There some interrupts labeled as QM_*, some even QM_PKT_DMA_*. So I would research, how do those events get generated, then study interrupt topology to understand, whether it could be routed as EDMA synchronization event.

Sorry, no ready to use solution.

Hi Rajarajan, 

Thank you for the information! 

I have looked through the description of these interrupts and how the interrupts are handled. I have two follow-up questions, if you could please take a look at them: 

1) The interrupts from Queue Manager send signals to CPU and require CPU's (CorePac in this case, I assume) involvement. Is this correct? Can we send the interrupt signal to another device, like an FPGA or does the CPU receive the interrupt first?

Is there no other way of sending "receive or transfer completion" signal from the PKTDMA to EDMA (for instance) without involving the CPU, as in "chaining" event functionality of EDMA3?

2) According to the description, the highlighted interrupts are for indicating the condition of "starvation" - when the receive flow is out of buffers and can't handle the incoming packets. It's different from "receive of packets is complete" indication, isn't it?

Thanks!

Hi,

One may think, that device consists of corepacks, peripherals, interconnects, but also interrupt controllers, which are normally not shown on device functional diagram. My point is that many system events can get routed to corepack directly, or through interrupt controller. Moreover, interrupt controller can make signals not only to corepack, but to peripheral like EDMA3.

Take a look at interrupt topology at https://www.ti.com/lit/ds/symlink/tms320c6678.pdf?ts=1652260100367&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTMS320C6678#%5B%7B%22num%22%3A459%2C%22gen%22%3A0%7D%2C%7B%22name%22%3A%22XYZ%22%7D%2C54%2C695%2Cnull%5D. Though not sure that is ever possible, one should look whether QM is producing any event, which can be served as CIC input event. Then if that could be CIC2, CIC3, one may route them as input events to EDMA3. Otherwise processor's ISR is needed to do the job.

Hi, 

Okay, now I understand. According to the documentation and the interrupt topology, it may be possible to send interrupt from QM to EDMA3 via CIC2 or CIC3. 

However, I can't find any system event from Table 7-40 in the DSP's datasheet (SPRS691E) that would indicate DM's PKTDMA packet receive completion. The "starvation" is not the same thing so QM_INT_PKTDMA_0 and QM_INT_PKTDMA_1 interrupts wouldn't work for this purpose. 

I am now looking at other QM_ interrupts from this table (QM_INT_HIGH_16 and such) to see what they actually do since the description "QM interrupt" doesn't tell anything. However, I can't find which register in QM needs to be set when dealing with these interrupts as shown in the table. 

Can you please give some idea on this? :) 

Thanks!

Hi Rajarajan, 

Thanks for the response. 

But I believe that this API doesn't handle the transfer completion interrupt between the Packet DMA (inside Queue Manager) and EDMA3 (two separate modules). 

This functionality ("chaining" and "transfer completion" as described in the API) is for the channels inside the EDMA3 module. 

I would like to know which interrupts of QM Packet DMA can be used to start EDMA3. 

Thanks!

Hi Islombek,

I believe your scenario has been used in Security Accelerator(SA) example in TI-RTOS SDK. I will check the code and provide the response ASAP.

Thanks,

Rajarajan U

Hi,

I really have no expertise in QM, of no help here. Instead, may I ask you to share your findings with community.

No problem. I am still looking into the documentation and it's very difficult to follow since information needs to be searched in lots and lots of documents. 

Thanks.

Hi Rajarajan, 

Thanks, but I have already seen this API as the QMSS driver is already implemented for Packet DMA transfers from NETCP. 
I wanted to get information on how QMSS can send interrupt to either EDMA3 on this DSP or to another chip on my board (FPGA) as soon as an Ethernet frame is received by NETCP or as soon as the frame is stored to the buffer by Packet DMA. 

Any suggestions? 

Thanks.

Islombek,

The functionality of the NETCP and QMSS are well demonstrated in the PDK example, "cppi_evmc6678_c66BiosExampleProject" . This example is part of Processor SDK 6.3 - Link to download - PROCESSOR-SDK-RTOS-C667x  06_03_00_106

This CPPI is the working example on C6678 board. 

Please have a look at the code sequence and check whether it matches your requirement.

Master FAQ - C6678 - https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1082264/faq-tms320c6678-quick-set-up-guide-c6678-and-c6678-evm/4005920#4005920

How to generate the CPPI PDK example - https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1082251/faq-tms320c6678-how-to-generate-the-ccs-pdk-examples-for-c6678

Regards

Shankari G

Thanks for the response, 

So far I have found 0 information that matches my requirement. 

Let me change the requirement and maybe you have some information on whether this new requirement is possible: 

Is there a way to signal/indicate to another device (such as an FPGA connected to the DSP) every time an Ethernet frame is received in GbE switch of Network Coprocessor? I don't want to involve the Core's. Maybe something via other peripherals? 
 

Islombek,

Thanks for your clear cut response

We will forward your query to the management and try to get some help for you.

Thanks for your patience...

Regards

Shankari

Hi, thanks for the response, 

As mentioned before, the EDMA chaining will not work as the received Ethernet frames are transferred using the Packet DMA of Network Coprocessor and Queue Manager. I saw that you can send interrupt to an EDMA channel or to CorePac via CIC, but the information on event and interrupt mapping is very difficult fo find. 

That's why I changed my requirement/question and see whether there was a way to send indication to another device when an Ethernet frame is received in the Ethernet Switch Subsystem? Please find the question in bold in the previous reply to your colleague Shankari. 

Kind regards, 

Hi again,

If I go ahead and pursue this route: configure an interrupt (by mapping Queue Manager event as input to CIC and mapping the CIC's output as input to EDMA3CC), can you tell me which events should be mapped to what?

I can't find a good documentation that connects the various events. 

For example, I see that in Table 7-40 in SPRS691E there are QM interrupts QM_INT_HIGH_0 to QM_INT_HIGH_15. The description just says "QM interrupt". In what condition or when do these interrupts occur? 


I can also see that supposedly these interrupts can be routed as input events to CIC2 (according Table 7-40 description). The "Configuring Interrupts on Keystone Devices" Wiki PDF shows that the CIC2 output events can be mapped to EDMA3CC2 input events to trigger EDMA3CC2 channels. 

Can you help me find out how to map, for example, QM_INT_HIGH_0 as input to CIC2 and how to map output of CIC2 as input to EDMA3CC2?
And can you help me with finding out when do these "QM interrupts" occur?

Thanks!