TDA4VM: How to enable OSPI flash 4Byte Mode?

Hi,

Tongxin Wang said:

We tried Define  EXT_ADDRESS_ENABLE in packages/ti/board/src/flash/nor/device/m35xu512.h , but sbl could not load sysfw from SBL_SysFwLoad() .  Is there any suggestion ?

What errors do you see while loading the sysfw? Can you share the logs?

Regards,
Parth

there are some steps we did in pdk: 

1. we tried to use the default ospi.cfg arg:

SBL Revision: 01.00.10.00 (May 24 2022 - 06:57:23)
Ospi Read speed for 0x200 bytes from offset 0x3900000 = 6 Mbytes per sec
TIFS  ver: 21.1.1--v2021.01a (Terrific Lla
SCISERVER Board Configuration header population... PASSED
Sciclient_setBoardConfigHeader... PASSED
Efuse xlated: VD 2 to 800 mV (OppVid: 0x37, Slave:0x48, Res:0x0)
Successfully set voltage to 800 mV for Slave:0x48, Res:0x0
Initlialzing PLLs ...done.
InitlialzingClocks ...done.
[xxx] in sbl_main, set ospi reset pin(A23) high
Initlialzing DDR ...done.
Initializing GTC ...Begin parsing user application
Calling Sciclient_procBootRequestProcessor, ProcId 0x20... 
Calling Sciclient_procBootRequestProcessor, ProcId 0x21... 
Calling Sciclient_procBootRequestProcessor, ProcId 0x1... 
Calling Sciclient_procBootRequestProcessor, ProcId 0x2... 
Calling Sciclient_procBootRequestProcessor, ProcId 0x6... 
Calling Sciclient_procBootRequestProcessor, ProcId 0x7... 
Calling Sciclient_procBootRequestProcessor, ProcId 0x8... 
Calling Sciclient_procBootRequestProcessor, ProcId 0x9... 
Calling Sciclient_procBootRequestProcessor, ProcId 0x3... 
Calling Sciclient_procBootRequestProcessor, ProcId 0x4... 
Calling Sciclient_procBootRequestProcessor, ProcId 0x30... 
ospiFunClk = 133333333 Hz 
[xxx] in SBL_ospiInit(), force dac = 1, phy = 1, dtr = 1, cache = 1, baudRateDiv = 6
Board_flashOpen failed!

2. we solve the problem 1 by doing following change. but we can only read ospi flash's 16MiB data . Since the 4 byte is not enable.

     ospi_cfg.dtrEnable = false;
     ospi_cfg.phyEnable = false;
     ospi_cfg.cacheEnable = false;;
     enableTuning = false;
     ospi_cfg.baudRateDiv = 6;
    SBL_log(SBL_LOG_ERR, "[xxx] in SBL_ospiInit(),  dac = %d, phy = %d, dtr = %d, cache = %d, baudRateDiv = %d\n", \
            ospi_cfg.dacEnable, ospi_cfg.phyEnable, ospi_cfg.dtrEnable, ospi_cfg.cacheEnable, ospi_cfg.baudRateDiv);

    /* Set the default SPI init configurations */
    OSPI_socSetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);


    h = Board_flashOpen(BOARD_FLASH_ID_MT35XU01GBBA1G12,
                            BOARD_OSPI_NOR_INSTANCE, (void *)(&enableTuning));

3. So , we base the setp 2  did following change to enable 4 byte address mode.

diff --git a/packages/ti/board/src/flash/nor/device/m35xu512.h b/packages/ti/board/src/flash/nor/device/m35xu512.h
index dde48e5..99bc817 100644
--- a/packages/ti/board/src/flash/nor/device/m35xu512.h
+++ b/packages/ti/board/src/flash/nor/device/m35xu512.h
@@ -48,7 +48,7 @@
  **************************************************************************/
 
 /** Macro to enable 4 byte addressing */
-/* #define EXT_ADDRESS_ENABLE        (0U) */
+ //#define EXT_ADDRESS_ENABLE        (0U) 
 
 /** FLASH device specific items (note: sizes are in bytes) */
 #define NOR_BLOCK_SIZE               (128U * 1024U)
@@ -92,16 +92,16 @@
 #define NOR_CMD_FAST_READ            (0x0BU)
 #define NOR_CMD_OCTAL_O_FAST_RD      (0x8BU)
 #define NOR_CMD_OCTAL_IO_FAST_RD     (0xCBU)
-#define NOR_CMD_OCTAL_DDR_O_FAST_RD  (0x9DU)
-#define NOR_CMD_OCTAL_DDR_IO_FAST_RD (0xFDU)
 #define NOR_CMD_OCTAL_READ           (NOR_CMD_OCTAL_O_FAST_RD)
 #define NOR_CMD_PAGE_PROG            (0x02U)
 #define NOR_CMD_OCTAL_FAST_PROG      (0x82U)
 #define NOR_CMD_EXT_OCTAL_FAST_PROG  (0xC2U)
 #define NOR_CMD_OCTAL_PROG           (NOR_CMD_OCTAL_FAST_PROG)
+#endif
+#define NOR_CMD_OCTAL_DDR_O_FAST_RD  (0x9DU)
+#define NOR_CMD_OCTAL_DDR_IO_FAST_RD (0xFDU)
 #define NOR_CMD_WRITE_VCR            (0x81U)
 #define NOR_CMD_READ_VCR             (0x85U)
-#endif
 
 /* \brief Read ID command definitions */
 #define NOR_RDID_NUM_BYTES           (0x3U)
 

@@ -151,7 +151,7 @@ static NOR_STATUS Nor_ospiEnableDDR(SPI_Handle handle)
                   (0 << 23)                         | /* read data disable */
                   (7 << 20)                         | /* read 8 data bytes */
                   (1 << 19)                         | /* enable cmd adddr */
-                  (2 << 16)                         | /* 3 address bytes */
+                  (3 << 16)                         | /* 4 address bytes */^M
                   (1 << 15);                          /* write data enable */
         data[1] = 0;     /* Non-volatile config register address */
         data[2] = 0xE7U; /* set to Octal DDR in Nonvolatile Config Reg 0x0 */

and we met the "TIFS load...FAILED" problem .

SBL Revision: 01.00.10.00 (May 24 2022 - 06:57:23)
Ospi Read speed for 0x200 bytes from offset 0x3900000 = 6 Mbytes per sec
TIFS load...FAILED

I put a wrong patch for setp3: 

in m35xu512.h 

diff --git a/packages/ti/board/src/flash/nor/device/m35xu512.h b/packages/ti/board/src/flash/nor/device/m35xu512.h
index dde48e5..99bc817 100644
--- a/packages/ti/board/src/flash/nor/device/m35xu512.h
+++ b/packages/ti/board/src/flash/nor/device/m35xu512.h
@@ -48,7 +48,7 @@
  **************************************************************************/
 
 /** Macro to enable 4 byte addressing */
-/* #define EXT_ADDRESS_ENABLE        (0U) */
+ #define EXT_ADDRESS_ENABLE        (0U) 
 
 /** FLASH device specific items (note: sizes are in bytes) */
 #define NOR_BLOCK_SIZE               (128U * 1024U)
@@ -92,16 +92,16 @@
 #define NOR_CMD_FAST_READ            (0x0BU)
 #define NOR_CMD_OCTAL_O_FAST_RD      (0x8BU)
 #define NOR_CMD_OCTAL_IO_FAST_RD     (0xCBU)
-#define NOR_CMD_OCTAL_DDR_O_FAST_RD  (0x9DU)
-#define NOR_CMD_OCTAL_DDR_IO_FAST_RD (0xFDU)
 #define NOR_CMD_OCTAL_READ           (NOR_CMD_OCTAL_O_FAST_RD)
 #define NOR_CMD_PAGE_PROG            (0x02U)
 #define NOR_CMD_OCTAL_FAST_PROG      (0x82U)
 #define NOR_CMD_EXT_OCTAL_FAST_PROG  (0xC2U)
 #define NOR_CMD_OCTAL_PROG           (NOR_CMD_OCTAL_FAST_PROG)
+#endif
+#define NOR_CMD_OCTAL_DDR_O_FAST_RD  (0x9DU)
+#define NOR_CMD_OCTAL_DDR_IO_FAST_RD (0xFDU)
 #define NOR_CMD_WRITE_VCR            (0x81U)
 #define NOR_CMD_READ_VCR             (0x85U)
-#endif
 
 /* \brief Read ID command definitions */
 #define NOR_RDID_NUM_BYTES           (0x3U)

Hi,

Did you re flash the binaries after making the above changes? Were you able to flash without any issues?

Regards,
Parth

Yes,I re flashed the binaries file to the ospi flash using the uboot sf cmd without any issues.

So I think the driver in uboot works well, but the driver provided in pdk are not working correctly. 

Hi,

I'll try to enable for 4 byte addressing at my end and get back to you. Meanwhile, can you try running OSPI driver example (Using any boot mode other than OSPI boot) and see if that is working fine.

Regards,
Parth