TDA4VM: PCIE reference clock externally

yongliang li

Intellectual 490 points

Part Number: TDA4VM

According to the routing PCIE reference clock externally, I set the PCIE clock to the external reference clock.

From the results of the read and write registers, it has been set successfully,

but in /sys/kernel/config/pci_ep/controller,there is no ep device.

I have three requestion:

1、how to change resistors to "PCIe end point" clock configuration?

2、How the external reference clock is connected in hardware

3、Are there any other settings, including device tree, kernel configuration, etc.

tda4vm(as ep device) sdk=ti-processor-sdk-linux-j7-evm-08_00_00_08-Linux-x86-Install.bin(linux kernel version=5.10.41)

I change the device tree(k3-j721e-common-proc-board.dts). disable pcie0-2 rc model,enable pcie0-2 ep model

over 3 years ago

0 jian35385 over 3 years ago

TI__Mastermind 23125 points

Yongliang,

The FAQ is for PCIe RC configuration where the REFCLK is provided by the TDA4VM device.

From above description, I assume you are using the TDA4VM as an PCIe end-point. So answers below are based on this assumption:

1、how to change resistors to "PCIe end point" clock configuration?

[Jian] please follow the notes in the Common Processor Board Schematics:

https://www.ti.com/lit/zip/sprr411

You will be look for sections named "CLOCK ROOT SELECTION " and you will need to use the "PCIe end point" configurations for each port.

2、How the external reference clock is connected in hardware

[Jian] The schematics give the example - where in EP mode, REFCLK is supplied from the PCIe connector coming from the host.

3、Are there any other settings, including device tree, kernel configuration, etc.

[Jian] Please follow notes under:

https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/08_02_00_03/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/PCIe/PCIe_End_Point.html

where steps are explained to 1). setup the clock configuration as EP on the EVM; 2). device tree modifications from default SDK (SDK defaults to RC); 3). How to test.

Please also note that this page captured steps to interconnect two EVMs, where one is RC and the other is EP. In this example, both RC and EP use their own refclk (distributed clocking configuration).

If your intention is to connect the TDA4 EVM to another host, say, an X86 PC, you will need to ignore the RESET signal, and power up the TDA4 EVM first. On clocking, you can use the SDK defaults, where hardware resistor changes disconnected the clock-gen source if there are REFCLK from the slot, then in TDA4, the SOC uses internal refclk for the EP also.

let me know if need further details.

regards

Jian

0 yongliang li over 3 years ago in reply to jian35385

Intellectual 490 points

Our design architecture is as follows, we want to use an external clock chip to provide 100MHz clock frequency to PCIE EP and PCIE RC devices at the same time. we use TDA4VM as PCIE EP device in PCIE1 x2 LANE（SERDES1）

my question is :

1.When TDA4VM is used as an EP device, does it use an external reference clock by default? If not how to configure it to use an external reference clock?

2.Regarding the hardware connection, we directly connect the output pin of the clock chip to the reference clock pin of SERDES1. But on the EVM board, when used as an EP device, resistors and capacitors are added to the external clock and SERDES1 reference clock pins. Is this necessary?

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TDA4VM: PCIE reference clock externally