[FAQ] TDA4VM: TDA4VM/DRA829V: routing PCIE reference clock externally

TDA4VM/DRA829V supports multiple PCIe reference clock (refclk) configurations, where each of the SERDES reference clock can be supplied from either external input or from on-chip PLL output. Additionally, the SOC can output standard 100MH reference clocks to driven external devices.

With these configurations, system integrators can create PCIe interconnections based on either Common Reference Clock or Separate (distributed) Reference Clock architecture.

This article explains how to route the PCIe refclk externally, and how to test it on the TDA4VM/DRA829 EVM. 

By default, the EVM and stock Linux SDK software uses the following configuration:

• The x1Lane and x2Lane interfaces are configured using "PCIe root complex" option, as shown in the EVM Common Processor Schematics. With this configuration, an external clock generator device supplies the refclk to the PCIe slot, used by the device plugged into the slots. The same refclk is also supplied to the TDA4VM SOC, but the SDK software does not use this clock source, instead, it uses internal PLL clock source for each of PCIe SERDES. So effectively, both PCIe slots uses Distributed Clock architecture. 
• The NVME slot (pcie2) uses "Clock Gen" option as shown in the EVM schematics, where the refclk on the slot is driven by the clock generator device on the EVM, and TDA4VM device uses internal PLL clock as the refclk for its SERDES, similar to the X1 and 2Lane slots.

To route the TDA4VM refclk to the PCIe slot, and test on the EVM, the following steps are needed:

1. Perform resistor modification on the EVM, to route TDA4VM refclk to the PCIe slots:

• for x1Lane and x2Lane slots, change resistors to "PCIe end point" clock configuration
• for the NVME slot, change resistor configurations to the "SOC" configuration

2. Apply the out-of-tree patch as attached in this article to Linux PCIe driver source code.  This patch perform the following tasks:

• Enables differential clock buffers ACSPCIe
• Select SERDES output as the input to the clock buffers

       Note that since the SERDES are already using internal PLL ouputs, all we did with the patch was just to route the SERDES clock to the REFCLK IO buffers then enables them. 

3.  (optional) If for any reason the end-point device is not recognized, perform a manual rescan of the PCIe interface, by issuing following commands on the Linux prompt:

     echo 1 > /sys/bus/pci/devices/0002:00:00.0/remove  (shown NVME node, replace the device node if using other slots)

     echo 1 > /sys/bus/pci/rescan

4. By now the PCIe device shall be clocked by the TDA4VM.

In case of debug and testing, the following registers shall be checked using devmem2 utility on the Linux command prompt (using NVME slot as example, update register address if other other slots):

·        //enable PADs of ACSPCIe

devmem2 0x00118094 reads 0x01000000 as expected.

·        //refclk select for ACSPCIe

devmem2 0x00108078 read 0x00000100 as expected.

Patch for SDK7.3:

 /cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_route_2D00_clock_2D00_externally.patch

Patch for SDK8.x:

/cfs-file/__key/communityserver-discussions-components-files/791/pcie_2D00_ref_2D00_clock_2D00_out_5F00_sdk8.diff