• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 97 subscribers
  • Views 928 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

[FAQ] TDA4VM: TDA4VM/DRA829V: routing PCIE reference clock externally

[FAQ] TDA4VL-Q1: J721S2XSOMXEVM: Routing PCIe reference clock externally

Takuma Fujiwara
Guru 50173 points
Part Number: TDA4VL-Q1
Other Parts Discussed in Thread: TDA4VL, TDA4VM, J721S2XSOMXEVM

Similar to TDA4VM, the TDA4VL supports multiple PCIe reference clock (refclk) configurations, where each of the SERDES reference clock can be supplied from either external input or from on-chip PLL output. Additionally, the SOC can output standard 100MH reference clocks to driven external devices.

With these configurations, system integrators can create PCIe interconnections based on either Common Reference Clock or Separate (distributed) Reference Clock architecture.

This article explains how to route the PCIe refclk externally, and how to test it on the TDA4VL on the J721S2XSOMXEVM board.

  • 0
    TI__Guru 50173 points

    Following instructions reference the schematic files that can be obtained from the "Design Files" section for CPB (Common Processor Board), and SOM (System On Module) board for J721S2:

    Hardware changes needed for TI EVM were:

    1. On common processor board, install R3, R4, C1, C2 and remove R1, R2, R5, R6 in below schematic file, such that SOC_SERDES1_REFCLK_P/N are connected to CON_PCIE1_2L_REFCLK_P/N:

    2. On SOM board, remove R16, R17 and install R20, R21, R19, R18, such that PCIE_REFCLK1_OUT_P/N are connected to SOC_SERDES0_REFCLK_P/N. R20, R21 is the same resistor as R16, R17, while R19, R18 are 49.9Ohm resistors with 1% tolerance:

    3. Optionally, to increase number of lanes. Remove C35, C36, R7, R8, C7, C8, C9, C10 and connect C32, C33, R9, R10, C13, C14, C16, C16 in below schematics:

    For software changes:

    1. Enabling ACSPCIe with 100MHz clock from MAIN_PLL2_HSDIV4_CLKOUT should make PCIe functional. Apply this patch on the Linux kernel in board-support/linux-* of PSDK Linux:  0001-enable-internal-refclk-for-J721S2-PCIe.patch

    Regards,

    Takuma