Hi TI,
Your suggestion last time as below:
. Offline Brijesh Jadav 1 month ago in reply to shawn lin
TI__Guru** 118865 points
Hi shawn lin,
If you enable single display and dsi output, does it work fine? Wanted to check if DSI works fine in standalone case.
Let me check your defaults.c file and get back to you.
Regards,
Brijesh
We try to enable single display and dsi output with 4 lane, but it doen't work.
We have also implement the path file as below to enable 4 lane:
The code where we modify and run vision_apps_init.sh as below:
app_cfg_mcu2_0.h:
#define ENABLE_DSS_SINGLE
#undef ENABLE_DSS_DUAL
#define ENABLE_DSS_DSI
#undef ENABLE_CSI2TX
app_init.c :
#ifdef ENABLE_DSS_DSI
prm.display_type = APP_DSS_DEFAULT_DISPLAY_TYPE_DSI;
prm.timings.width = 1280U;
prm.timings.height = 800U;
prm.timings.hFrontPorch = 110U;
prm.timings.hBackPorch = 220U;
prm.timings.hSyncLen = 40U;
prm.timings.vFrontPorch = 5U;
prm.timings.vBackPorch = 20U;
prm.timings.vSyncLen = 5U;
prm.timings.pixelClock = 74250000ULL;
#endif
status = appDssDefaultInit(&prm);
APP_ASSERT_SUCCESS(status);
}
app_dss_defaults.c :
if(obj->initPrm.display_type==APP_DSS_DEFAULT_DISPLAY_TYPE_DSI)
{
/* Only two lanes output supported for AOU LCD */
dsiParams.num_lanes = 4u;
retVal+= appRemoteServiceRun(cpuId, APP_DCTRL_REMOTE_SERVICE_NAME, APP_DCTRL_CMD_SET_DSI_PARAMS, &dsiParams, sizeof(dsiParams), 0U);
}
main.c(vision_apps/apps/dl_demos/app_tidl/main.c) :
if ((vx_true_e == tivxIsTargetEnabled(TIVX_TARGET_DISPLAY1)) && (obj->display_option == 1))
{
obj->disp_image = vxCreateImage(obj->context, DISPLAY_WIDTH, DISPLAY_HEIGHT, VX_DF_IMAGE_RGB);
APP_ASSERT_VALID_REF(obj->disp_image)
obj->image_addr.dim_x = DISPLAY_WIDTH;
obj->image_addr.dim_y = DISPLAY_HEIGHT;
obj->image_addr.stride_x = 3; /* RGB */
obj->image_addr.stride_y = DISPLAY_WIDTH * 3;
obj->image_addr.scale_x = VX_SCALE_UNITY;
obj->image_addr.scale_y = VX_SCALE_UNITY;
obj->image_addr.step_x = 1;
obj->image_addr.step_y = 1;
obj->disp_rect.start_x = 0;
obj->disp_rect.start_y = 0;
obj->disp_rect.end_x = DISPLAY_WIDTH;
obj->disp_rect.end_y = DISPLAY_HEIGHT;
memset(&obj->disp_params, 0, sizeof(tivx_display_params_t));
obj->disp_params.opMode = TIVX_KERNEL_DISPLAY_BUFFER_COPY_MODE;
obj->disp_params.pipeId = 0;
obj->disp_params.outWidth = DISPLAY_WIDTH;
obj->disp_params.outHeight = DISPLAY_HEIGHT;
obj->disp_params.posX = (1280-DISPLAY_WIDTH)/2;
obj->disp_params.posY = (800-DISPLAY_HEIGHT)/2;
obj->disp_params_obj = vxCreateUserDataObject(obj->context, "tivx_display_params_t", sizeof(tivx_display_params_t), &obj->disp_params);
APP_ASSERT_VALID_REF(obj->disp_params_obj)
tivxHwaLoadKernels(obj->context);
}
app_common.h :
#define MAX_IMG_WIDTH (2048) #define MAX_IMG_HEIGHT (1024) #define DISPLAY_WIDTH (1280) #define DISPLAY_HEIGHT (800) #define NUM_CH (1) #define NUM_ALGOS (5)
Run vision_apps_init.sh show as below:
[MCU2_0] 3.564561 s: CIO: Init ... Done !!! [MCU2_0] 3.564615 s: ### CPU Frequency = 1000000000 Hz [MCU2_0] 3.564646 s: APP: Init ... !!! [MCU2_0] 3.564665 s: SCICLIENT: Init ... !!! [MCU2_0] 3.564871 s: SCICLIENT: DMSC FW version [21.5.0--v2021.05 (Terrific Llam] [MCU2_0] 3.564914 s: SCICLIENT: DMSC FW revision 0x15 [MCU2_0] 3.564939 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU2_0] 3.564966 s: SCICLIENT: Init ... Done !!! [MCU2_0] 3.564988 s: UDMA: Init ... !!! [MCU2_0] 3.566042 s: UDMA: Init ... Done !!! [MCU2_0] 3.566090 s: MEM: Init ... !!! [MCU2_0] 3.566125 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e1000000 of size 16777216 bytes !!! [MCU2_0] 3.566178 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 262144 bytes !!! [MCU2_0] 3.566227 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ d8000000 of size 16777216 bytes !!! [MCU2_0] 3.566272 s: MEM: Init ... Done !!! [MCU2_0] 3.566293 s: IPC: Init ... !!! [MCU2_0] 3.566349 s: IPC: 6 CPUs participating in IPC !!! [MCU2_0] 3.566390 s: IPC: Waiting for HLOS to be ready ... !!! [MCU2_0] 18.197427 s: IPC: HLOS is ready !!! [MCU2_0] 18.202651 s: IPC: Init ... Done !!! [MCU2_0] 18.202701 s: APP: Syncing with 5 CPUs ... !!! [MCU2_0] 19.636563 s: APP: Syncing with 5 CPUs ... Done !!! [MCU2_0] 19.636607 s: REMOTE_SERVICE: Init ... !!! [MCU2_0] 19.637916 s: REMOTE_SERVICE: Init ... Done !!! [MCU2_0] 19.638015 s: ETHFW: Init ... !!! [MCU2_0] 19.656926 s: CPSW_9G Test on MAIN NAVSS [MCU2_0] 19.670395 s: ETHFW: Version : 0.01.01 [MCU2_0] 19.670453 s: ETHFW: Build Date: Aug 12, 2021 [MCU2_0] 19.670484 s: ETHFW: Build Time: 11:51:44 [MCU2_0] 19.670506 s: ETHFW: Commit SHA: fc8c791d [MCU2_0] 19.670561 s: ETHFW: Init ... DONE !!! [MCU2_0] 19.670589 s: ETHFW: Remove server Init ... !!! [MCU2_0] 19.671348 s: Remote demo device (core : mcu2_0) ..... [MCU2_0] 19.671400 s: ETHFW: Remove server Init ... DONE !!! [MCU2_0] 19.672279 s: Starting lwIP, local interface IP is dhcp-enabled [MCU2_0] 19.678007 s: Host MAC address: 70:ff:76:1d:92:c2 [MCU2_0] 19.721339 s: FVID2: Init ... !!! [MCU2_0] 19.721434 s: FVID2: Init ... Done !!! [MCU2_0] 19.721477 s: DSS: Init ... !!! [MCU2_0] 19.721502 s: DSS: Display type is DSI !!! [MCU2_0] 19.721526 s: DSS: M2M Path is enabled !!! [MCU2_0] 19.721549 s: DSS: SoC init ... !!! [MCU2_0] 19.721568 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2 [MCU2_0] 19.721735 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 19.721770 s: SCICLIENT: Sciclient_pmSetModuleState module=150 state=2 [MCU2_0] 19.721885 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 19.721913 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2 [MCU2_0] 19.722003 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 19.722034 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=9 parent=11 [MCU2_0] 19.722118 s: SCICLIENT: Sciclient_pmSetModuleClkParent success [MCU2_0] 19.722150 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=152 clk=9 freq=74250000 [MCU2_0] 19.723135 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success [MCU2_0] 19.723177 s: SCICLIENT: Sciclient_pmModuleClkRequest module=152 clk=9 state=2 flag=0 [MCU2_0] 19.723292 s: SCICLIENT: Sciclient_pmModuleClkRequest success [MCU2_0] 19.723374 s: DSS: SoC init ... Done !!! [MCU2_0] 19.725877 s: DSS: Init ... Done !!! [MCU2_0] 19.725933 s: VHWA: VPAC Init ... !!! [MCU2_0] 19.725962 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2 [MCU2_0] 19.726120 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 19.726155 s: VHWA: LDC Init ... !!! [MCU2_0] 19.729300 s: VHWA: LDC Init ... Done !!! [MCU2_0] 19.729421 s: VHWA: MSC Init ... !!! [MCU2_0] 19.738849 s: VHWA: MSC Init ... Done !!! [MCU2_0] 19.738910 s: VHWA: NF Init ... !!! [MCU2_0] 19.740553 s: VHWA: NF Init ... Done !!! [MCU2_0] 19.740603 s: VHWA: VISS Init ... !!! [MCU2_0] 19.750491 s: VHWA: VISS Init ... Done !!! [MCU2_0] 19.750543 s: VHWA: VPAC Init ... Done !!! [MCU2_0] 19.750584 s: VX_ZONE_INIT:Enabled [MCU2_0] 19.750612 s: VX_ZONE_ERROR:Enabled [MCU2_0] 19.750634 s: VX_ZONE_WARNING:Enabled [MCU2_0] 19.751647 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target IPU1-0 [MCU2_0] 19.751836 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_NF [MCU2_0] 19.752012 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_LDC1 [MCU2_0] 19.752188 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_MSC1 [MCU2_0] 19.752484 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_MSC2 [MCU2_0] 19.752719 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_VISS1 [MCU2_0] 19.752937 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE1 [MCU2_0] 19.753165 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE2 [MCU2_0] 19.753476 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DISPLAY1 [MCU2_0] 19.753730 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DISPLAY2 [MCU2_0] 19.753926 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CSITX [MCU2_0] 19.754158 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE3 [MCU2_0] 19.754487 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE4 [MCU2_0] 19.754727 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE5 [MCU2_0] 19.754960 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE6 [MCU2_0] 19.755196 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE7 [MCU2_0] 19.755508 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE8 [MCU2_0] 19.755726 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DSS_M2M1 [MCU2_0] 19.755914 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DSS_M2M2 [MCU2_0] 19.756100 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DSS_M2M3 [MCU2_0] 19.756280 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DSS_M2M4 [MCU2_0] 19.756450 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [MCU2_0] 19.756484 s: APP: OpenVX Target kernel init ... !!! [MCU2_0] 19.768302 s: APP: OpenVX Target kernel init ... Done !!! [MCU2_0] 19.768450 s: CSI2RX: Init ... !!! [MCU2_0] 19.768476 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2 [MCU2_0] 19.768578 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 19.768616 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2 [MCU2_0] 19.768720 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 19.768750 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2 [MCU2_0] 19.768838 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 19.768868 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2 [MCU2_0] 19.768936 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 19.768965 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2 [MCU2_0] 19.769028 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 19.769775 s: CSI2RX: Init ... Done !!! [MCU2_0] 19.769829 s: ISS: Init ... !!! [MCU2_0] 19.769868 s: IssSensor_Init ... Done !!! [MCU2_0] 19.769964 s: vissRemoteServer_Init ... Done !!! [MCU2_0] 19.770032 s: IttRemoteServer_Init ... Done !!! [MCU2_0] 19.770064 s: UDMA Copy: Init ... !!! [MCU2_0] 19.771668 s: UDMA Copy: Init ... Done !!! [MCU2_0] 19.771759 s: APP: Init ... Done !!! [MCU2_0] 19.771792 s: APP: Run ... !!! [MCU2_0] 19.771815 s: IPC: Starting echo test ... [MCU2_0] 19.773931 s: APP: Run ... Done !!! [MCU2_0] 19.775207 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[.] C66X_2[.] C7X_1[.] [MCU2_0] 19.775299 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[.] C66X_2[P] C7X_1[.] [MCU2_0] 19.775489 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[.] C66X_2[P] C7X_1[P] [MCU2_0] 19.781386 s: [LWIPIF_LWIP] NETIF INIT SUCCESS [MCU2_0] 19.781446 s: Added interface 'ti1', IP is 0.0.0.0 [MCU2_0] 19.896881 s: Function:CpswProxyServer_attachExtHandlerCb,HostId:0,CpswType:6 [MCU2_0] 21.831595 s: Function:CpswProxyServer_registerMacHandlerCb,HostId:0,Handle:a2fb6054,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c1, FlowIdx:172, FlowIdxOffset:0 [MCU2_0] 21.834670 s: Cpsw_ioctlInternal: CPSW: Registered MAC address.ALE entry:12, Policer Entry:1 [MCU2_1] 3.572594 s: CIO: Init ... Done !!! [MCU2_1] 3.572649 s: ### CPU Frequency = 1000000000 Hz [MCU2_1] 3.572681 s: APP: Init ... !!! [MCU2_1] 3.572700 s: SCICLIENT: Init ... !!! [MCU2_1] 3.572898 s: SCICLIENT: DMSC FW version [21.5.0--v2021.05 (Terrific Llam] [MCU2_1] 3.572935 s: SCICLIENT: DMSC FW revision 0x15 [MCU2_1] 3.572958 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU2_1] 3.572982 s: SCICLIENT: Init ... Done !!! [MCU2_1] 3.573004 s: UDMA: Init ... !!! [MCU2_1] 3.574043 s: UDMA: Init ... Done !!! [MCU2_1] 3.574090 s: MEM: Init ... !!! [MCU2_1] 3.574121 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e2000000 of size 16777216 bytes !!! [MCU2_1] 3.574172 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3640000 of size 262144 bytes !!! [MCU2_1] 3.574227 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ d9000000 of size 117440512 bytes !!! [MCU2_1] 3.574275 s: MEM: Init ... Done !!! [MCU2_1] 3.574295 s: IPC: Init ... !!! [MCU2_1] 3.574341 s: IPC: 6 CPUs participating in IPC !!! [MCU2_1] 3.574379 s: IPC: Waiting for HLOS to be ready ... !!! [MCU2_1] 19.631324 s: IPC: HLOS is ready !!! [MCU2_1] 19.636471 s: IPC: Init ... Done !!! [MCU2_1] 19.636524 s: APP: Syncing with 5 CPUs ... !!! [MCU2_1] 19.636562 s: APP: Syncing with 5 CPUs ... Done !!! [MCU2_1] 19.636590 s: REMOTE_SERVICE: Init ... !!! [MCU2_1] 19.637904 s: REMOTE_SERVICE: Init ... Done !!! [MCU2_1] 19.638010 s: FVID2: Init ... !!! [MCU2_1] 19.638075 s: FVID2: Init ... Done !!! [MCU2_1] 19.638105 s: VHWA: DMPAC: Init ... !!! [MCU2_1] 19.638126 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2 [MCU2_1] 19.638278 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 19.638312 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2 [MCU2_1] 19.638416 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 19.638442 s: VHWA: DOF Init ... !!! [MCU2_1] 19.646141 s: VHWA: DOF Init ... Done !!! [MCU2_1] 19.646187 s: VHWA: SDE Init ... !!! [MCU2_1] 19.648444 s: VHWA: SDE Init ... Done !!! [MCU2_1] 19.648486 s: VHWA: DMPAC: Init ... Done !!! [MCU2_1] 19.648521 s: VX_ZONE_INIT:Enabled [MCU2_1] 19.648545 s: VX_ZONE_ERROR:Enabled [MCU2_1] 19.648565 s: VX_ZONE_WARNING:Enabled [MCU2_1] 19.649464 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DMPAC_SDE [MCU2_1] 19.649633 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DMPAC_DOF [MCU2_1] 19.649685 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [MCU2_1] 19.649715 s: APP: OpenVX Target kernel init ... !!! [MCU2_1] 19.649916 s: APP: OpenVX Target kernel init ... Done !!! [MCU2_1] 19.649950 s: UDMA Copy: Init ... !!! [MCU2_1] 19.651451 s: UDMA Copy: Init ... Done !!! [MCU2_1] 19.651502 s: APP: Init ... Done !!! [MCU2_1] 19.651528 s: APP: Run ... !!! [MCU2_1] 19.651548 s: IPC: Starting echo test ... [MCU2_1] 19.653410 s: APP: Run ... Done !!! [MCU2_1] 19.654297 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[.] C7X_1[.] [MCU2_1] 19.654388 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[.] [MCU2_1] 19.654466 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P] [MCU2_1] 19.774969 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P] [C6x_1 ] 3.705158 s: CIO: Init ... Done !!! [C6x_1 ] 3.705182 s: ### CPU Frequency = 1350000000 Hz [C6x_1 ] 3.705192 s: APP: Init ... !!! [C6x_1 ] 3.705200 s: SCICLIENT: Init ... !!! [C6x_1 ] 3.705387 s: SCICLIENT: DMSC FW version [21.5.0--v2021.05 (Terrific Llam] [C6x_1 ] 3.705400 s: SCICLIENT: DMSC FW revision 0x15 [C6x_1 ] 3.705410 s: SCICLIENT: DMSC FW ABI revision 3.1 [C6x_1 ] 3.705421 s: SCICLIENT: Init ... Done !!! [C6x_1 ] 3.705430 s: UDMA: Init ... !!! [C6x_1 ] 3.706634 s: UDMA: Init ... Done !!! [C6x_1 ] 3.706656 s: MEM: Init ... !!! [C6x_1 ] 3.706668 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e4000000 of size 16777216 bytes !!! [C6x_1 ] 3.706685 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!! [C6x_1 ] 3.706701 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e5000000 of size 50331648 bytes !!! [C6x_1 ] 3.706717 s: MEM: Init ... Done !!! [C6x_1 ] 3.706725 s: IPC: Init ... !!! [C6x_1 ] 3.706744 s: IPC: 6 CPUs participating in IPC !!! [C6x_1 ] 3.706758 s: IPC: Waiting for HLOS to be ready ... !!! [C6x_1 ] 16.141306 s: IPC: HLOS is ready !!! [C6x_1 ] 16.144728 s: IPC: Init ... Done !!! [C6x_1 ] 16.144755 s: APP: Syncing with 5 CPUs ... !!! [C6x_1 ] 19.636562 s: APP: Syncing with 5 CPUs ... Done !!! [C6x_1 ] 19.636578 s: REMOTE_SERVICE: Init ... !!! [C6x_1 ] 19.637231 s: REMOTE_SERVICE: Init ... Done !!! [C6x_1 ] 19.637270 s: VX_ZONE_INIT:Enabled [C6x_1 ] 19.637282 s: VX_ZONE_ERROR:Enabled [C6x_1 ] 19.637292 s: VX_ZONE_WARNING:Enabled [C6x_1 ] 19.638135 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [C6x_1 ] 19.638153 s: APP: OpenVX Target kernel init ... !!! [C6x_1 ] 19.638433 s: APP: OpenVX Target kernel init ... Done !!! [C6x_1 ] 19.638454 s: UDMA Copy: Init ... !!! [C6x_1 ] 19.641663 s: UDMA Copy: Init ... Done !!! [C6x_1 ] 19.641682 s: APP: Init ... Done !!! [C6x_1 ] 19.642347 s: APP: Run ... !!! [C6x_1 ] 19.642359 s: IPC: Starting echo test ... [C6x_1 ] 19.643543 s: APP: Run ... Done !!! [C6x_1 ] 19.643861 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[s] C66X_2[P] C7X_1[.] [C6x_1 ] 19.643893 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_1 ] 19.654087 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_1 ] 19.774890 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_2 ] 3.809905 s: CIO: Init ... Done !!! [C6x_2 ] 3.809931 s: ### CPU Frequency = 1350000000 Hz [C6x_2 ] 3.809941 s: APP: Init ... !!! [C6x_2 ] 3.809949 s: SCICLIENT: Init ... !!! [C6x_2 ] 3.810138 s: SCICLIENT: DMSC FW version [21.5.0--v2021.05 (Terrific Llam] [C6x_2 ] 3.810151 s: SCICLIENT: DMSC FW revision 0x15 [C6x_2 ] 3.810161 s: SCICLIENT: DMSC FW ABI revision 3.1 [C6x_2 ] 3.810171 s: SCICLIENT: Init ... Done !!! [C6x_2 ] 3.810180 s: UDMA: Init ... !!! [C6x_2 ] 3.811377 s: UDMA: Init ... Done !!! [C6x_2 ] 3.811401 s: MEM: Init ... !!! [C6x_2 ] 3.811413 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e8000000 of size 16777216 bytes !!! [C6x_2 ] 3.811431 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!! [C6x_2 ] 3.811446 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e9000000 of size 50331648 bytes !!! [C6x_2 ] 3.811462 s: MEM: Init ... Done !!! [C6x_2 ] 3.811470 s: IPC: Init ... !!! [C6x_2 ] 3.811489 s: IPC: 6 CPUs participating in IPC !!! [C6x_2 ] 3.811502 s: IPC: Waiting for HLOS to be ready ... !!! [C6x_2 ] 17.237314 s: IPC: HLOS is ready !!! [C6x_2 ] 17.240634 s: IPC: Init ... Done !!! [C6x_2 ] 17.240660 s: APP: Syncing with 5 CPUs ... !!! [C6x_2 ] 19.636562 s: APP: Syncing with 5 CPUs ... Done !!! [C6x_2 ] 19.636577 s: REMOTE_SERVICE: Init ... !!! [C6x_2 ] 19.637234 s: REMOTE_SERVICE: Init ... Done !!! [C6x_2 ] 19.637273 s: VX_ZONE_INIT:Enabled [C6x_2 ] 19.637283 s: VX_ZONE_ERROR:Enabled [C6x_2 ] 19.637292 s: VX_ZONE_WARNING:Enabled [C6x_2 ] 19.638119 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [C6x_2 ] 19.638134 s: APP: OpenVX Target kernel init ... !!! [C6x_2 ] 19.638418 s: APP: OpenVX Target kernel init ... Done !!! [C6x_2 ] 19.638439 s: UDMA Copy: Init ... !!! [C6x_2 ] 19.641549 s: UDMA Copy: Init ... Done !!! [C6x_2 ] 19.641567 s: APP: Init ... Done !!! [C6x_2 ] 19.642247 s: APP: Run ... !!! [C6x_2 ] 19.642258 s: IPC: Starting echo test ... [C6x_2 ] 19.643357 s: APP: Run ... Done !!! [C6x_2 ] 19.643643 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[x] C66X_2[s] C7X_1[P] [C6x_2 ] 19.643851 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[s] C7X_1[P] [C6x_2 ] 19.654106 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P] [C6x_2 ] 19.774905 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P] [C7x_1 ] 4.034381 s: CIO: Init ... Done !!! [C7x_1 ] 4.034395 s: ### CPU Frequency = 1000000000 Hz [C7x_1 ] 4.034407 s: APP: Init ... !!! [C7x_1 ] 4.034414 s: SCICLIENT: Init ... !!! [C7x_1 ] 4.034584 s: SCICLIENT: DMSC FW version [21.5.0--v2021.05 (Terrific Llam] [C7x_1 ] 4.034598 s: SCICLIENT: DMSC FW revision 0x15 [C7x_1 ] 4.034608 s: SCICLIENT: DMSC FW ABI revision 3.1 [C7x_1 ] 4.034618 s: SCICLIENT: Init ... Done !!! [C7x_1 ] 4.034627 s: UDMA: Init ... !!! [C7x_1 ] 4.035502 s: UDMA: Init ... Done !!! [C7x_1 ] 4.035513 s: MEM: Init ... !!! [C7x_1 ] 4.035523 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ 100000000 of size 268435456 bytes !!! [C7x_1 ] 4.035545 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!! [C7x_1 ] 4.035563 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 491520 bytes !!! [C7x_1 ] 4.035580 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!! [C7x_1 ] 4.035596 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ ec000000 of size 268435456 bytes !!! [C7x_1 ] 4.035614 s: MEM: Init ... Done !!! [C7x_1 ] 4.035622 s: IPC: Init ... !!! [C7x_1 ] 4.035634 s: IPC: 6 CPUs participating in IPC !!! [C7x_1 ] 4.035648 s: IPC: Waiting for HLOS to be ready ... !!! [C7x_1 ] 18.249340 s: IPC: HLOS is ready !!! [C7x_1 ] 18.251292 s: IPC: Init ... Done !!! [C7x_1 ] 18.251306 s: APP: Syncing with 5 CPUs ... !!! [C7x_1 ] 19.636563 s: APP: Syncing with 5 CPUs ... Done !!! [C7x_1 ] 19.636579 s: REMOTE_SERVICE: Init ... !!! [C7x_1 ] 19.636922 s: REMOTE_SERVICE: Init ... Done !!! [C7x_1 ] 19.636945 s: VX_ZONE_INIT:Enabled [C7x_1 ] 19.636957 s: VX_ZONE_ERROR:Enabled [C7x_1 ] 19.636967 s: VX_ZONE_WARNING:Enabled [C7x_1 ] 19.637198 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [C7x_1 ] 19.637212 s: APP: OpenVX Target kernel init ... !!! [C7x_1 ] 19.637307 s: APP: OpenVX Target kernel init ... Done !!! [C7x_1 ] 19.637330 s: APP: Init ... Done !!! [C7x_1 ] 19.637342 s: APP: Run ... !!! [C7x_1 ] 19.637350 s: IPC: Starting echo test ... [C7x_1 ] 19.637875 s: APP: Run ... Done !!! [C7x_1 ] 19.643656 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[x] C66X_2[P] C7X_1[s] [C7x_1 ] 19.643866 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[P] C7X_1[s] [C7x_1 ] 19.654127 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s] [C7x_1 ] 19.774934 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s]
