AM625: IPC Mechanisms

Hello,

What version of software are you trying to run on the AM62x A53 and the M4F? I am not familiar with Cdd. This response will be based on the RPMsg based IPC which is documented in the AM62x Linux Processor SDK (https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/08_03_00_19/exports/docs/linux/Foundational_Components_IPC62x.html).

Yes, RPMsg IPC uses virtio.

At this point in time, I have not run IPC benchmark tests on AM62x. Does your system have any specific requirements for the IPC? (latency, throughput, etc?)

For a deeper dive on designing a system that has required cycle times, reference https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1085663/faq-sitara-multicore-system-design-how-to-ensure-computations-occur-within-a-set-cycle-time

"not all mailbox interrupts can be routed to all cores": for example on AM62x, the PRU cores do not have the same mailbox connection as M4F cores. PRU RPMsg uses interrupts instead of mailboxes to notify the A53.

Regards,

Nick

Hi Nick,

Thank you for your response. 

Do you recommend any specific version of the Software to run and test?

By CDD I refer to the document attached, in my first thread. Can TI confirm that this doc is not from TI (My hint was there were some Intranet links referred) or it is not relevant?

1. Is the Linux side developed solution already available, and was it tested in conjunction with Autosar than FreeRTOS by chance by TI?
2. Under the section (document attached), Queue in shared memory; it is mentioned as below
   1. It could be possible that one processor (producer) might generate faster IPC messages than another processor (consumer). To avoid messages being over-written/lost an shared queue shall be implemented in the shared buffer
   2. What are the sizes of queues and buffers and at which stage?

And will there be any chance in near future you would be able to provide the benchmarks?

Hello Nick ,

By PRU cores - Programmable real time unit cores u mean the R5F cores ,In this case R5F doesn't use mailbox (pre configured interrupts for process) ? 

If so how do the PRU cores trigger these interrupts (by RPNOTIFY )? and are these hardware interrupts?

Hello Charulatha & Ajithkumar,

IPC software that is currently enabled

You can find the software packages that TI currently provides for AM62x in the Design & Development > Software Development section of the AM625 product page: https://www.ti.com/product/AM625#software-development . These are the software releases that TI has tested.

Keep in mind that TI is a big company with many different processors and products. In this case, the document you linked is for different software on a different group's processor - it looks like Jacinto? If you are interested in using a TDA part instead of the AM62x, I would suggest creating a different thread that would be assigned to the Jacinto team.

Just to be explicit: the RPMsg IPC that we have currently enabled for AM62x is between the A53 core (Linux) and the M4F core (FreeRTOS or NORTOS).

What about the PRU?

The PRU cores in the PRU Subsystem are different from R5F. Please reference the datasheet, TRM, and Linux SDK documentation for more details about the PRU.

If you look at the MCU+ SDK release notes, you will see what features are supported for the M4F core. The M4F does not support loading & communicating with the PRU: https://software-dl.ti.com/mcu-plus-sdk/esd/AM62X/08_03_00_07/exports/docs/api_guide_am62x/RELEASE_NOTES_08_03_00_PAGE.html

What about the AM62x R5F? 

The AM62x R5F is a dedicated device and power manager. We do not enable R5F development on AM62x. See the datasheet for more information.

Autosar on AM62x? 

I am reassigning your thread to another team member to comment on AM62x Autosar.

Regards,

Nick

Hello,

This IPC CDD has not been tested with Autosar. The MCAL IPC CDD drivers are not yet available.

Thanks

Yogesh