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Original question:

AM625: MAIN, MCU and WKUP Domain Communication Interfaces of AM6252

AM625: Power-Up Sequencing: Power-On RESET Timing (MCU_PORz)

Utku Uygun
Prodigy 155 points
Part Number: AM625
Other Parts Discussed in Thread: TPS3897

Hi,

According to the datasheet of the AM6252, reset timing section, 9500000 ns hold time is required after all supplies valid. But I cannot see any delay part in the reference design schematics. How does the reference design ensure this hold time?

In addition, we do not plan to use the following signals which is used to manage the MCU_PORz in the reference design:

  • TEST_PORZn
  • VCC_5V0_PG
  • JTAG_EMU_RSTn
  • SoC_PORz
  • CONN_MCU_PORz

Thats why I only want to use 0.85V (VDDR_CORE) regulator power good (PG) output to assert the MCU_PORz signal.

Is it appropriate to directly use just 0.85V PG output for PORz asserting? In that case, should we use RC delay circuit etc. on the MCU_PORz line to provide 9500000 ns hold time?

Thanks for your help in advance.

  • 0
    TI__Guru*** 137548 points

    Hello Utku Uygun

    Thank you for the query. 

    Let me check internally and update you.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru*** 137548 points

    Hello Utku Uygun

    Thats why I only want to use 0.85V (VDDR_CORE) regulator power good (PG) output to assert the MCU_PORz signal.

    Is it appropriate to directly use just 0.85V PG output for PORz asserting? In that case, should we use RC delay circuit etc. on the MCU_PORz line to provide 9500000 ns hold time?

    Using an RC delay circuit is will likely violate the min slew rate defined in the System Timing Conditions table of the datasheet. You might have to do some signal conditioning. 

    Alternatively, You can consider TPS3897 or similar Supervisory Circuit  with adjustable timing for the delay,

    Regards,

     Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Prodigy 155 points

    Hi Kallikuppa,

    As I understood, the reference design uses signal conditioning but I didn't understand how it provides the time delay of 9500000 ns after all supplies are valid. Could you please help me to understand it?

  • +1 in reply to Utku Uygun
    TI__Guru*** 137548 points

    Hello Utku Uygun

    Thank you for the note.

    Not sue if i understand what you meant by signal conditioning. Could you please elaborate.

    Please note that we do not consider our hardware platforms to be a reference design. They are evaluation platforms and may not represent a proper system implementation. 

    Our EVM design sometimes outpaces our ability to fully understand device requirements. This is done so the hardware platform is available when first silicon arrives.  We may learn new device requirements during processor bring-up and bench validation.  If so, these new requirements may not be accounted for in our hardware development platform.  Therefore, TI expects customers to carefully review and follow all requirements defined in the datasheet, silicon errata, and TRM when designing their system.  Our hardware development platforms were not designed to be comprehensive of specific system requirements

    Regard,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Prodigy 155 points

    Hi,

    Thanks for your support. I get your point, we will continue with TPS3897 or an another similar IC for our design.

    Kind regards,

    Utku UYGUN 

  • 0 in reply to Utku Uygun
    TI__Guru*** 137548 points

    Hello Utku Uygun

    Thank you for the note. You have a great weekend.

    Regards,

    Sreenivasa