TDA4VM: Boot and run Mcu Island MCU_R5Fs app in lockstep mode from SBL

Tan Yang

Prodigy 10 points

Part Number: TDA4VM

Hi TI experters,

I'm using LAUTERBACH to debug Mcu Island R5F software based on ti-processor-sdk-rtos-j721e-evm-08_00_00_12.

When boot MCU island R5F cores from NorFlash, i expect the R5F cores will run in lock step mode.

[Observation]:

1. When hook in SBL before run SCI services, i see the Mcu Island R5F cores runs lock step mode by observing CTRLMMR_MCUSEC_CLSTR0_CFG

After Mcu Island R5F core requested SCI services, i observed the register CTRLMMR_MCUSEC_CLSTR0_CFG becomes all ZERO.

- seems either its run in split mode ?

- or still run in local step mode but due to some reason the register is not accessible from debugger anymore ?

over 3 years ago

0 Brijesh Jadav over 3 years ago

TI__Guru**** 477995 points

Hi,

Can you please refer to below link for setting R5F in lockstep mode?

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1008069/faq-tda4vm-enable-mcu_r5f-lockstep-using-spl-and-sbl

Regards,

Brijesh

0 Richard Woodruff over 3 years ago in reply to Brijesh Jadav

TI__Mastermind 23665 points

Hello,

I believe the effect you are seeing is a result of the firmware execution changing accessibility. Before firmware that space can be read by M3:SD:0x45950000, R5:SD:0x45950000, or debugger (AXI:0x45950000). After the firmware the space can only be read by DMSC/M3 local accesses SD:0x45950000.

The system design has the firmware owning this space so clients after the firmware is running will need to make SCI calls to work with these registers. A debug correlation check can still be done but it has to be done from the M3 perspective. If your firmware gives debug access permissions to the M3, you can dump it in an M3 instance, or make an Intercom evaluate to pass the value back to your R5 instance.

Regards,

Richard W.

Processors

Processors forum

TDA4VM: Boot and run Mcu Island MCU_R5Fs app in lockstep mode from SBL