Hi, TI
my sdk version is as below:
ti-processor-sdk-linux-j7-evm-08_02_00_03
ti-processor-sdk-rtos-j721e-evm-08_02_00_05
I'm testing the DSI port on TDA4VM EVM board and there is no disaply on the screen after I run the demo ./run_apps_dof.sh. no input signal from the screen uart logs.
By the way, it works with eDP port with the same demo app.
TDA4VM DSI ----> UB941 -----> UB928 ------> LCD
I have done some modifications as below:
1、Part1，enable dsi port and config timming to 1080p, dump ub941 register, change the lan number the 941 config.
diff --git a/vision_apps/platform/j721e/rtos/common/app_cfg_mcu2_0.h b/vision_apps/platform/j721e/rtos/common/app_cfg_mcu2_0.h
index 066f2683..c92e0136 100755
--- a/vision_apps/platform/j721e/rtos/common/app_cfg_mcu2_0.h
+++ b/vision_apps/platform/j721e/rtos/common/app_cfg_mcu2_0.h
@@ -76,7 +76,8 @@
#ifdef BUILD_MCU_BOARD_DEPENDENCIES
#define ENABLE_CSI2RX
- #define ENABLE_CSI2TX
+ // #define ENABLE_CSI2TX
+ #undef ENABLE_CSI2TX //dsi prot
/* IMPORANT NOTE:
* - Only one of ENABLE_DSS_SINGLE or ENABLE_DSS_DUAL should be defined
@@ -88,14 +89,16 @@
/* define below to enable eDP display,
make sure to undef ENABLE_DSS_HDMI & ENABLE_DSS_DSI as well */
- #define ENABLE_DSS_EDP
+ // #define ENABLE_DSS_EDP //yongfeng.liu
+ #undef ENABLE_DSS_EDP //yongfeng.liu
/* define below to enable HDMI display,
make sure to undef ENABLE_DSS_EDP & ENABLE_DSS_DSI as well */
#undef ENABLE_DSS_HDMI
/* define below to enable DSI display, make sure to undef ENABLE_DSS_HDMI
& ENABLE_DSS_EDP as well */
- #undef ENABLE_DSS_DSI
-
+ // #undef ENABLE_DSS_DSI //dsi prot
+ #define ENABLE_DSS_DSI //dsi prot
+
#define ENABLE_I2C
#define ENABLE_BOARD
diff --git a/vision_apps/platform/j721e/rtos/common/app_init.c b/vision_apps/platform/j721e/rtos/common/app_init.c
index 34d33e37..45124562 100755
--- a/vision_apps/platform/j721e/rtos/common/app_init.c
+++ b/vision_apps/platform/j721e/rtos/common/app_init.c
@@ -550,15 +550,25 @@ int32_t appInit()
#ifdef ENABLE_DSS_DSI
prm.display_type = APP_DSS_DEFAULT_DISPLAY_TYPE_DSI;
- prm.timings.width = 1280U;
- prm.timings.height = 800U;
- prm.timings.hFrontPorch = 110U;
- prm.timings.hBackPorch = 220U;
- prm.timings.hSyncLen = 40U;
- prm.timings.vFrontPorch = 5U;
- prm.timings.vBackPorch = 20U;
+ // prm.timings.width = 1280U;
+ // prm.timings.height = 800U;
+ // prm.timings.hFrontPorch = 110U;
+ // prm.timings.hBackPorch = 220U;
+ // prm.timings.hSyncLen = 40U;
+ // prm.timings.vFrontPorch = 5U;
+ // prm.timings.vBackPorch = 20U;
+ // prm.timings.vSyncLen = 5U;
+ // prm.timings.pixelClock = 74250000ULL;
+
+ prm.timings.width = 1920U;
+ prm.timings.height = 1080U;
+ prm.timings.hFrontPorch = 88U;
+ prm.timings.hBackPorch = 148U;
+ prm.timings.hSyncLen = 44U;
+ prm.timings.vFrontPorch = 4U;
+ prm.timings.vBackPorch = 36U;
prm.timings.vSyncLen = 5U;
- prm.timings.pixelClock = 74250000ULL;
+ prm.timings.pixelClock = 61875000;
#endif
status = appDssDefaultInit(&prm);
APP_ASSERT_SUCCESS(status);
diff --git a/vision_apps/utils/dss/src/app_dss_defaults.c b/vision_apps/utils/dss/src/app_dss_defaults.c
index ddfda3a9..2072b61f 100755
--- a/vision_apps/utils/dss/src/app_dss_defaults.c
+++ b/vision_apps/utils/dss/src/app_dss_defaults.c
@@ -347,8 +347,11 @@ int32_t appDctrlDefaultInit(app_dss_default_obj_t *obj)
retVal = appRemoteServiceRun(cpuId, APP_DCTRL_REMOTE_SERVICE_NAME, APP_DCTRL_CMD_REGISTER_HANDLE, &doHpd, sizeof(doHpd), 0U);
if(obj->initPrm.display_type==APP_DSS_DEFAULT_DISPLAY_TYPE_DSI)
{
+ #if 0
/* Only two lanes output supported for AOU LCD */
dsiParams.num_lanes = 2u;
+ #endif
+ dsiParams.num_lanes = 4u; //yfliu
retVal+= appRemoteServiceRun(cpuId, APP_DCTRL_REMOTE_SERVICE_NAME, APP_DCTRL_CMD_SET_DSI_PARAMS, &dsiParams, sizeof(app_dctrl_dsi_params_t), 0U);
}
diff --git a/vision_apps/utils/dss/src/app_dss_j721e.c b/vision_apps/utils/dss/src/app_dss_j721e.c
index c0f70d1b..0e1858ef 100755
--- a/vision_apps/utils/dss/src/app_dss_j721e.c
+++ b/vision_apps/utils/dss/src/app_dss_j721e.c
@@ -84,9 +84,10 @@ uint8_t Ub941Ub925Config[][4] = {
{0x16, 0x40, 0x09, 0x5},
{0x16, 0x41, 0x21, 0x5},
{0x16, 0x42, 0x60, 0x5},
-{0x16, 0x5b, 0x85, 0x5},
-{0x16, 0x4f, 0x8c, 0x5},
-{0x16, 0x4f, 0x84, 0x5},
+// {0x16, 0x5b, 0x85, 0x5},
+{0x16, 0x5b, 0x81, 0x5}, /*single mode*/
+{0x16, 0x4f, 0x8c, 0x5}, /*4 lans*/
+// {0x16, 0x4f, 0x84, 0x5}, /*2 lans*/
{0x16, 0x40, 0x05, 0x5},
{0x16, 0x40, 0x04, 0x5},
{0x16, 0x41, 0x05, 0x5},
@@ -266,6 +267,30 @@ void appDssConfigureDP(void)
}
}
+void UB941AndUB925Dump(void *handle)
+{
+ int i,ret;
+ uint8_t regData = 0;
+
+ appLogPrintf("dump ub941 registers begin\n");
+ for(i=0; i<256; i++)
+ {
+ ret = Board_i2c8BitRegRd(handle,
+ 0x16,//fpdModParams->serSlvAddr,
+ i,
+ ®Data,
+ 1U,
+ BOARD_I2C_TRANSACTION_TIMEOUT);
+ if(ret != 0)
+ {
+ return;
+ }
+
+ appLogPrintf("0x%2x: 0x%2x\n",i,(unsigned char)(regData & 0xff));
+ }
+ appLogPrintf("dump ub941 registers done\n");
+}
+
void appDssConfigureUB941AndUB925(app_dss_default_prm_t *prm)
{
int32_t status;
@@ -301,6 +326,8 @@ void appDssConfigureUB941AndUB925(app_dss_default_prm_t *prm)
}
}
+ UB941AndUB925Dump(gI2cHandle);
+
I2C_close(gI2cHandle);
appLogPrintf("DSS: SERDES Configuration... Done !!!\n");
}
2. Part2 apply the patch
diff --git a/packages/ti/drv/dss/include/dss_dctrl.h b/packages/ti/drv/dss/include/dss_dctrl.h
index cafefd6..ad8bdd6 100755
--- a/packages/ti/drv/dss/include/dss_dctrl.h
+++ b/packages/ti/drv/dss/include/dss_dctrl.h
@@ -604,6 +604,12 @@ typedef struct
/**< DSI Instance ID, currently note used */
uint32_t numOfLanes;
/**< Number of outputs lanes for DSI output, max 4 */
+ uint32_t laneSpeedInKbps;
+ /**< Exact DPHY lane speed from the selected speed band in Megabits per sec.
+ * This parameter is set to default value during init time.
+ * If updated in the application after init, newly set value will be used
+ * for DPHY clock configurations.
+ */
} Dss_DctrlDsiParams;
/* ========================================================================== */
diff --git a/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlDsi.c b/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlDsi.c
index 162ee94..db3cae4 100755
--- a/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlDsi.c
+++ b/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlDsi.c
@@ -70,6 +70,7 @@
/* Base Address of DSI Wrapper */
#define DSITX2_WRAP_REGS_BASE (CSL_DSS_DSI0_DSI_WRAP_MMR_VBUSP_CFG_DSI_WRAP_BASE)
+#define DSITX_DPHY_REF_CLK_KHZ_DEF (19200U)
/* ========================================================================== */
/* Structure Declarations */
@@ -100,7 +101,22 @@ typedef struct
} Dss_DctrlDSIDrvObj;
-
+/**
+ * struct Dsitx_DphyRangeData
+ *
+ * \brief This structure holds information about DSI Tx Range. Typically used
+ * for DPHY programming.
+ *
+ */
+typedef struct
+{
+ uint32_t rangeMin;
+ /**< Lower boundary of the range */
+ uint32_t rangeMax;
+ /**< Hogher boundary of the range */
+ uint32_t progVal;
+ /**< Value to be programmed for given range */
+} Dsitx_DphyRangeData;
/* ========================================================================== */
/* Function Declarations */
@@ -128,6 +144,184 @@ extern "C" {
static Dss_DctrlDSIDrvObj gDssDctrlDsiDrvObj;
+/* This contains information of the PLL input divider value for DPHY
+ rangeMin and rangeMax is in KHz */
+
+static Dsitx_DphyRangeData gDsiTxIpDivInfo[] =
+{
+ {
+ .rangeMin = 9600U,
+ .rangeMax = 19200U,
+ .progVal = 1U,
+ },
+ {
+ .rangeMin = 19200U,
+ .rangeMax = 38400U,
+ .progVal = 2U,
+ },
+ {
+ .rangeMin = 38400U,
+ .rangeMax = 76800U,
+ .progVal = 4U,
+ },
+ {
+ .rangeMin = 76800U,
+ .rangeMax = 150000U,
+ .progVal = 8U,
+ },
+};
+
+/* This contains information of the PLL output divider value for DPHY
+ rangeMin and rangeMax is in Mbps */
+static Dsitx_DphyRangeData gDsiTxOpDivInfo[] =
+{
+ {
+ .rangeMin = 1250U,
+ .rangeMax = 2500U,
+ .progVal = 1U,
+ },
+ {
+ .rangeMin = 630U,
+ .rangeMax = 1240U,
+ .progVal = 2U,
+ },
+ {
+ .rangeMin = 320U,
+ .rangeMax = 620U,
+ .progVal = 4U,
+ },
+ {
+ .rangeMin = 160U,
+ .rangeMax = 310U,
+ .progVal = 8U,
+ },
+ {
+ .rangeMin = 80U,
+ .rangeMax = 150U,
+ .progVal = 16U,
+ },
+};
+
+/* This contains information of the PLL output divider value for DPHY
+ rangeMin and rangeMax is in Mbps */
+static Dsitx_DphyRangeData gDsiTxLaneSpeedBandInfo[] =
+{
+ {
+ .rangeMin = 80U,
+ .rangeMax = 100U,
+ .progVal = 0x0,
+ },
+ {
+ .rangeMin = 100U,
+ .rangeMax = 120U,
+ .progVal = 0x1,
+ },
+ {
+ .rangeMin = 120U,
+ .rangeMax = 160U,
+ .progVal = 0x2,
+ },
+ {
+ .rangeMin = 160U,
+ .rangeMax = 200U,
+ .progVal = 0x3,
+ },
+ {
+ .rangeMin = 200U,
+ .rangeMax = 240U,
+ .progVal = 0x4,
+ },
+ {
+ .rangeMin = 240U,
+ .rangeMax = 320U,
+ .progVal = 0x5,
+ },
+ {
+ .rangeMin = 320U,
+ .rangeMax = 390U,
+ .progVal = 0x6,
+ },
+ {
+ .rangeMin = 390U,
+ .rangeMax = 450U,
+ .progVal = 0x7,
+ },
+ {
+ .rangeMin = 450U,
+ .rangeMax = 510U,
+ .progVal = 0x8,
+ },
+ {
+ .rangeMin = 510U,
+ .rangeMax = 560U,
+ .progVal = 0x9,
+ },
+ {
+ .rangeMin = 560U,
+ .rangeMax = 640U,
+ .progVal = 0xA,
+ },
+ {
+ .rangeMin = 640U,
+ .rangeMax = 690U,
+ .progVal = 0xB,
+ },
+ {
+ .rangeMin = 690U,
+ .rangeMax = 770U,
+ .progVal = 0xC,
+ },
+ {
+ .rangeMin = 770U,
+ .rangeMax = 870U,
+ .progVal = 0xD,
+ },
+ {
+ .rangeMin = 870U,
+ .rangeMax = 950U,
+ .progVal = 0xE,
+ },
+ {
+ .rangeMin = 950U,
+ .rangeMax = 1000U,
+ .progVal = 0xF,
+ },
+ {
+ .rangeMin = 1000U,
+ .rangeMax = 1200U,
+ .progVal = 0x10,
+ },
+ {
+ .rangeMin = 1200U,
+ .rangeMax = 1400U,
+ .progVal = 0x11,
+ },
+ {
+ .rangeMin = 1400U,
+ .rangeMax = 1600U,
+ .progVal = 0x12,
+ },
+ {
+ .rangeMin = 1600U,
+ .rangeMax = 1800U,
+ .progVal = 0x13,
+ },
+ {
+ .rangeMin = 1800U,
+ .rangeMax = 2000U,
+ .progVal = 0x14,
+ },
+ {
+ .rangeMin = 2000U,
+ .rangeMax = 2200U,
+ .progVal = 0x15,
+ },
+ {
+ .rangeMin = 2200U,
+ .rangeMax = 2500U,
+ .progVal = 0x16,
+ },
+};
/* ========================================================================== */
/* Internal/Private Function Declarations */
@@ -155,7 +349,7 @@ static int32_t dssDctrlEnableDsiLinkAndPath(Dss_DctrlDSIDrvObj *dsiObj);
static int32_t dssDctrlEnableDsiLink(Dss_DctrlDSIDrvObj *dsiObj);
static int32_t dssDctrlEnableDsiDatapath(Dss_DctrlDSIDrvObj *dsiObj);
static int32_t dssDctrlWaitForLaneReady(Dss_DctrlDSIDrvObj *dsiObj);
-
+static int32_t dssdctrlCalcDsiParams(Dss_DctrlDSIDrvObj *dsiObj, const Dss_DctrlDsiParams *dsiPrms);
/* ========================================================================== */
/* Function Definitions */
@@ -198,6 +392,8 @@ int32_t Dss_dctrlDrvSetDSIParams(Dss_DctrlDrvInfo *drvInfo,
dsiObj->cfgDsiTx.numOfLanes = dsiPrms->numOfLanes;
dsiObj->privDsiTx.numOfLanes = dsiPrms->numOfLanes;
+ status = dssdctrlCalcDsiParams(dsiObj, dsiPrms);
+
/* Checks to see if the configuration (num of lanes) is valid */
status = DSITX_Probe(&dsiObj->cfgDsiTx, &dsiObj->sysReqDsiTx);
if (CDN_EOK == status)
@@ -294,6 +490,105 @@ int32_t Dss_dctrlDrvEnableVideoDSI(Dss_DctrlDrvInfo *drvInfo,
/* Internal/Private Function Definitions */
/* ========================================================================== */
+static int32_t dssdctrlCalcDsiParams(Dss_DctrlDSIDrvObj *dsiObj, const Dss_DctrlDsiParams *dsiPrms)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t min, max;
+ uint32_t idx = 0U;
+ uint64_t tempResult, refClkKHz;
+
+ /* Get speed band for given lane speed */
+ for (idx = 0U ;
+ idx < (sizeof(gDsiTxLaneSpeedBandInfo) / sizeof(Dsitx_DphyRangeData));
+ idx++)
+ {
+ min = gDsiTxLaneSpeedBandInfo[idx].rangeMin * 1000;
+ max = gDsiTxLaneSpeedBandInfo[idx].rangeMax * 1000;
+ if ((dsiPrms->laneSpeedInKbps >= min) &&
+ (dsiPrms->laneSpeedInKbps <= max))
+ {
+ break;
+ }
+
+ }
+ if (idx < (sizeof(gDsiTxLaneSpeedBandInfo) / sizeof(Dsitx_DphyRangeData)))
+ {
+ dsiObj->dphyTxRate = (gDsiTxLaneSpeedBandInfo[idx].progVal) |
+ (gDsiTxLaneSpeedBandInfo[idx].progVal << 5);
+ }
+ else
+ {
+ retVal = FVID2_EFAIL;
+ }
+
+ if (retVal == FVID2_SOK)
+ {
+ /* TODO: Read the clock runtime through sciclient APIs */
+ refClkKHz = DSITX_DPHY_REF_CLK_KHZ_DEF;
+ /* Calculate DPHY ipdiv - PLL input divider */
+ if (retVal == FVID2_SOK)
+ {
+ for (idx = 0U ;
+ idx < (sizeof(gDsiTxIpDivInfo) / sizeof(Dsitx_DphyRangeData));
+ idx++)
+ {
+ if ((refClkKHz >= gDsiTxIpDivInfo[idx].rangeMin) &&
+ (refClkKHz < gDsiTxIpDivInfo[idx].rangeMax))
+ {
+ break;
+ }
+ }
+ if (idx < (sizeof(gDsiTxIpDivInfo) / sizeof(Dsitx_DphyRangeData)))
+ {
+ dsiObj->dphyTxIpDiv = gDsiTxIpDivInfo[idx].progVal;
+ }
+ else
+ {
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ /* Calculate DPHY opdiv - PLL output divider */
+ if (retVal == FVID2_SOK)
+ {
+ for (idx = 0U ;
+ idx < (sizeof(gDsiTxOpDivInfo) / sizeof(Dsitx_DphyRangeData));
+ idx++)
+ {
+ min = gDsiTxOpDivInfo[idx].rangeMin * 1000;
+ max = gDsiTxOpDivInfo[idx].rangeMax * 1000;
+ if ((dsiPrms->laneSpeedInKbps >= min) &&
+ (dsiPrms->laneSpeedInKbps <= max))
+ {
+ break;
+ }
+ }
+ if (idx < (sizeof(gDsiTxOpDivInfo) / sizeof(Dsitx_DphyRangeData)))
+ {
+ dsiObj->dphyTxOpDiv = gDsiTxOpDivInfo[idx].progVal;
+ }
+ else
+ {
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ /* Calculate DPHY fbdiv - PLL feedback divider */
+ if (retVal == FVID2_SOK)
+ {
+ tempResult = (((uint64_t)dsiPrms->laneSpeedInKbps) *
+ ((uint64_t)2U) *
+ ((uint64_t)dsiObj->dphyTxIpDiv) *
+ ((uint64_t)dsiObj->dphyTxOpDiv));
+ tempResult /= (uint64_t)refClkKHz;
+
+ dsiObj->dphyTxFbDiv = (uint32_t)tempResult;
+ }
+ }
+
+ return retVal;
+}
+
static void dssDctrlSetDSIInCtrlMod()
{
/*
3、uart logs after bring up. from which the ub941 register's value is dumped
root@j7-evm:~# cd /opt/vision_apps/ root@j7-evm:/opt/vision_apps# source ./vision_apps_init.sh root@j7-evm:/opt/vision_apps# [MCU2_0] 4.139456 s: CIO: Init ... Done !!! [MCU2_0] 4.139532 s: ### CPU Frequency = 1000000000 Hz [MCU2_0] 4.139579 s: APP: Init ... !!! [MCU2_0] 4.139607 s: SCICLIENT: Init ... !!! [MCU2_0] 4.139858 s: SCICLIENT: DMSC FW version [22.1.1--v2022.01 (Terrific Llam] [MCU2_0] 4.139911 s: SCICLIENT: DMSC FW revision 0x16 [MCU2_0] 4.139945 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU2_0] 4.139983 s: SCICLIENT: Init ... Done !!! [MCU2_0] 4.140012 s: UDMA: Init ... !!! [MCU2_0] 4.141283 s: UDMA: Init ... Done !!! [MCU2_0] 4.141347 s: MEM: Init ... !!! [MCU2_0] 4.141396 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d9000000 of size 16777216 bytes !!! [MCU2_0] 4.141480 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 262144 bytes !!! [MCU2_0] 4.141549 s: MEM: Init ... Done !!! [MCU2_0] 4.141578 s: IPC: Init ... !!! [MCU2_0] 4.141647 s: IPC: 6 CPUs participating in IPC !!! [MCU2_0] 4.141702 s: IPC: Waiting for HLOS to be ready ... !!! [MCU2_0] 16.693131 s: IPC: HLOS is ready !!! [MCU2_0] 16.708382 s: IPC: Init ... Done !!! [MCU2_0] 16.708453 s: APP: Syncing with 5 CPUs ... !!! [MCU2_0] 17.439377 s: APP: Syncing with 5 CPUs ... Done !!! [MCU2_0] 17.439597 s: REMOTE_SERVICE: Init ... !!! [MCU2_0] 17.441135 s: REMOTE_SERVICE: Init ... Done !!! [MCU2_0] 17.441216 s: ETHFW: Init ... !!! [MCU2_0] 17.461792 s: ETHFW: Shared multicasts (software fanout): [MCU2_0] 17.461872 s: 01:00:5e:00:00:01 [MCU2_0] 17.461928 s: 01:00:5e:00:00:fb [MCU2_0] 17.461979 s: 01:00:5e:00:00:fc [MCU2_0] 17.462029 s: 33:33:00:00:00:01 [MCU2_0] 17.462078 s: 33:33:ff:1d:92:c2 [MCU2_0] 17.462125 s: 01:80:c2:00:00:00 [MCU2_0] 17.462179 s: 01:80:c2:00:00:03 [MCU2_0] 17.462234 s: ETHFW: Reserved multicasts: [MCU2_0] 17.462263 s: 01:80:c2:00:00:0e [MCU2_0] 17.462312 s: 01:1b:19:00:00:00 [MCU2_0] 17.462570 s: EnetMcm: CPSW_9G on MAIN NAVSS [MCU2_0] 17.472239 s: PHY 16 is alive [MCU2_0] 17.472327 s: PHY 17 is alive [MCU2_0] 17.472381 s: PHY 18 is alive [MCU2_0] 17.472425 s: PHY 19 is alive [MCU2_0] 17.473149 s: EnetPhy_bindDriver: PHY 16: OUI:0001c1 Model:27 Ver:00 <-> 'vsc8514' : OK [MCU2_0] 17.473522 s: EnetPhy_bindDriver: PHY 17: OUI:0001c1 Model:27 Ver:00 <-> 'vsc8514' : OK [MCU2_0] 17.473844 s: EnetPhy_bindDriver: PHY 18: OUI:0001c1 Model:27 Ver:00 <-> 'vsc8514' : OK [MCU2_0] 17.474182 s: EnetPhy_bindDriver: PHY 19: OUI:0001c1 Model:27 Ver:00 <-> 'vsc8514' : OK [MCU2_0] 17.475926 s: [MCU2_0] ETHFW Version : 0.02.00 [MCU2_0] 17.476004 s: ETHFW Build Date: Jun 5, 2022 [MCU2_0] 17.476045 s: ETHFW Build Time: 10:38:06 [MCU2_0] 17.476077 s: ETHFW Commit SHA: 73d17a6c [MCU2_0] 17.476149 s: ETHFW: Init ... DONE !!! [MCU2_0] 17.476191 s: ETHFW: Remove server Init ... !!! [MCU2_0] 17.476377 s: CpswProxyServer: Virtual port configuration: [MCU2_0] 17.476438 s: mpu_1_0 <-> Switch port 0: mpu_1_0_ethswitch-device-0 [MCU2_0] 17.476487 s: mcu_2_1 <-> Switch port 1: mcu_2_1_ethswitch-device-1 [MCU2_0] 17.476533 s: mpu_1_0 <-> MAC port 1: mpu_1_0_ethmac-device-1 [MCU2_0] 17.476575 s: mcu_2_1 <-> MAC port 4: mcu_2_1_ethmac-device-4 [MCU2_0] 17.477627 s: CpswProxyServer: initialization completed (core: mcu2_0) [MCU2_0] 17.477702 s: ETHFW: Remove server Init ... DONE !!! [MCU2_0] 17.478842 s: Starting lwIP, local interface IP is dhcp-enabled [MCU2_0] 17.485389 s: Host MAC address: 70:ff:76:1d:92:c3 [MCU2_0] 17.489284 s: [LWIPIF_LWIP] Enet LLD netif initialized successfully [MCU2_0] 17.519836 s: [LWIPIF_LWIP_IC] Interface started successfully [MCU2_0] 17.519912 s: [LWIPIF_LWIP_IC] NETIF INIT SUCCESS [MCU2_0] 17.530189 s: FVID2: Init ... !!! [MCU2_0] 17.530298 s: FVID2: Init ... Done !!! [MCU2_0] 17.530357 s: DSS: Init ... !!! [MCU2_0] 17.530389 s: DSS: Display type is DSI !!! [MCU2_0] 17.530417 s: DSS: M2M Path is enabled !!! [MCU2_0] 17.530444 s: DSS: SoC init ... !!! [MCU2_0] 17.530470 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2 [MCU2_0] 17.530664 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 17.530709 s: SCICLIENT: Sciclient_pmSetModuleState module=150 state=2 [MCU2_0] 17.530867 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 17.530905 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2 [MCU2_0] 17.531030 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 17.531067 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=9 parent=11 [MCU2_0] 17.531292 s: SCICLIENT: Sciclient_pmSetModuleClkParent success [MCU2_0] 17.531352 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=152 clk=9 freq=61875000 [MCU2_0] 17.532452 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success [MCU2_0] 17.532511 s: SCICLIENT: Sciclient_pmModuleClkRequest module=152 clk=9 state=2 flag=0 [MCU2_0] 17.532681 s: SCICLIENT: Sciclient_pmModuleClkRequest success [MCU2_0] 17.532725 s: DSS: SoC init ... Done !!! [MCU2_0] 17.532754 s: DSS: Configuring SERDES ... !!! [MCU2_0] 17.554601 s: [LWIPIF_LWIP_IC] Interface started successfully [MCU2_0] 17.554678 s: [LWIPIF_LWIP_IC] NETIF INIT SUCCESS [MCU2_0] 17.554790 s: Added interface 'br4', IP is 0.0.0.0 [MCU2_0] 17.805192 s: DSS: Write Failed for ClientAddr 0x27 RegAddr 0x0 Value 0xfe ! [MCU2_0] 17.805286 s: dump ub941 registers begin [MCU2_0] 17.805463 s: 0x 0: 0x2c [MCU2_0] 17.805641 s: 0x 1: 0x 0 [MCU2_0] 17.805809 s: 0x 2: 0x 0 [MCU2_0] 17.805975 s: 0x 3: 0x9a [MCU2_0] 17.806140 s: 0x 4: 0x 0 [MCU2_0] 17.806429 s: 0x 5: 0x 0 [MCU2_0] 17.806610 s: 0x 6: 0x58 [MCU2_0] 17.806778 s: 0x 7: 0x58 [MCU2_0] 17.806942 s: 0x 8: 0x22 [MCU2_0] 17.807104 s: 0x 9: 0x 1 [MCU2_0] 17.807346 s: 0x a: 0x 7 [MCU2_0] 17.807531 s: 0x b: 0x 0 [MCU2_0] 17.807702 s: 0x c: 0x 3 [MCU2_0] 17.807866 s: 0x d: 0x30 [MCU2_0] 17.808026 s: 0x e: 0x 0 [MCU2_0] 17.808296 s: 0x f: 0x 0 [MCU2_0] 17.808486 s: 0x10: 0x 0 [MCU2_0] 17.808659 s: 0x11: 0x 0 [MCU2_0] 17.808826 s: 0x12: 0x 0 [MCU2_0] 17.808991 s: 0x13: 0xbb [MCU2_0] 17.809155 s: 0x14: 0x 0 [MCU2_0] 17.809434 s: 0x15: 0x 0 [MCU2_0] 17.809604 s: 0x16: 0xfe [MCU2_0] 17.809769 s: 0x17: 0x9e [MCU2_0] 17.809933 s: 0x18: 0x7f [MCU2_0] 17.810094 s: 0x19: 0x7f [MCU2_0] 17.810338 s: 0x1a: 0x 1 [MCU2_0] 17.810521 s: 0x1b: 0x 0 [MCU2_0] 17.810689 s: 0x1c: 0x 0 [MCU2_0] 17.810854 s: 0x1d: 0x 0 [MCU2_0] 17.811014 s: 0x1e: 0x 1 [MCU2_0] 17.811269 s: 0x1f: 0x 0 [MCU2_0] 17.811453 s: 0x20: 0x 3 [MCU2_0] 17.811618 s: 0x21: 0x 0 [MCU2_0] 17.811782 s: 0x22: 0x25 [MCU2_0] 17.811943 s: 0x23: 0x 0 [MCU2_0] 17.812103 s: 0x24: 0x 0 [MCU2_0] 17.812337 s: 0x25: 0x 0 [MCU2_0] 17.812522 s: 0x26: 0x 0 [MCU2_0] 17.812689 s: 0x27: 0x 0 [MCU2_0] 17.812851 s: 0x28: 0x 1 [MCU2_0] 17.813012 s: 0x29: 0x20 [MCU2_0] 17.813279 s: 0x2a: 0x20 [MCU2_0] 17.813463 s: 0x2b: 0xa0 [MCU2_0] 17.813632 s: 0x2c: 0x 0 [MCU2_0] 17.813795 s: 0x2d: 0x 0 [MCU2_0] 17.813958 s: 0x2e: 0xa5 [MCU2_0] 17.814118 s: 0x2f: 0x5a [MCU2_0] 17.814342 s: 0x30: 0x 0 [MCU2_0] 17.814524 s: 0x31: 0xb9 [MCU2_0] 17.814694 s: 0x32: 0x 0 [MCU2_0] 17.814862 s: 0x33: 0x 5 [MCU2_0] 17.815025 s: 0x34: 0x c [MCU2_0] 17.815277 s: 0x35: 0x 0 [MCU2_0] 17.815461 s: 0x36: 0x 0 [MCU2_0] 17.815629 s: 0x37: 0x 0 [MCU2_0] 17.815793 s: 0x38: 0x 0 [MCU2_0] 17.815954 s: 0x39: 0x 0 [MCU2_0] 17.816116 s: 0x3a: 0x 0 [MCU2_0] 17.816352 s: 0x3b: 0x 0 [MCU2_0] 17.816535 s: 0x3c: 0x 0 [MCU2_0] 17.816703 s: 0x3d: 0x 0 [MCU2_0] 17.816866 s: 0x3e: 0x81 [MCU2_0] 17.817027 s: 0x3f: 0x 2 [MCU2_0] 17.817281 s: 0x40: 0x 8 [MCU2_0] 17.817466 s: 0x41: 0x 5 [MCU2_0] 17.817636 s: 0x42: 0x c [MCU2_0] 17.817799 s: 0x43: 0x 0 [MCU2_0] 17.817961 s: 0x44: 0x 0 [MCU2_0] 17.818124 s: 0x45: 0x 0 [MCU2_0] 17.818393 s: 0x46: 0x 0 [MCU2_0] 17.818577 s: 0x47: 0x 0 [MCU2_0] 17.818747 s: 0x48: 0x 0 [MCU2_0] 17.818908 s: 0x49: 0x 0 [MCU2_0] 17.819068 s: 0x4a: 0x 0 [MCU2_0] 17.819335 s: 0x4b: 0x 0 [MCU2_0] 17.819517 s: 0x4c: 0x 0 [MCU2_0] 17.819683 s: 0x4d: 0x 0 [MCU2_0] 17.819846 s: 0x4e: 0x 0 [MCU2_0] 17.820008 s: 0x4f: 0x8c [MCU2_0] 17.820278 s: 0x50: 0x16 [MCU2_0] 17.820461 s: 0x51: 0x 0 [MCU2_0] 17.820632 s: 0x52: 0x 0 [MCU2_0] 17.820794 s: 0x53: 0x 0 [MCU2_0] 17.820955 s: 0x54: 0x 2 [MCU2_0] 17.821116 s: 0x55: 0x 0 [MCU2_0] 17.821337 s: 0x56: 0x 0 [MCU2_0] 17.821521 s: 0x57: 0x 2 [MCU2_0] 17.821687 s: 0x58: 0x 0 [MCU2_0] 17.821854 s: 0x59: 0x 0 [MCU2_0] 17.822016 s: 0x5a: 0x92 [MCU2_0] 17.822281 s: 0x5b: 0x81 [MCU2_0] 17.822471 s: 0x5c: 0x 7 [MCU2_0] 17.822645 s: 0x5d: 0x 6 [MCU2_0] 17.822812 s: 0x5e: 0x44 [MCU2_0] 17.822975 s: 0x5f: 0x 0 [MCU2_0] 17.823136 s: 0x60: 0x22 [MCU2_0] 17.823405 s: 0x61: 0x 2 [MCU2_0] 17.823594 s: 0x62: 0x 0 [MCU2_0] 17.823763 s: 0x63: 0x 0 [MCU2_0] 17.823927 s: 0x64: 0x 4 [MCU2_0] 17.824089 s: 0x65: 0x 1 [MCU2_0] 17.824343 s: 0x66: 0x 3 [MCU2_0] 17.824534 s: 0x67: 0x 3 [MCU2_0] 17.824702 s: 0x68: 0x 0 [MCU2_0] 17.824865 s: 0x69: 0x 0 [MCU2_0] 17.825027 s: 0x6a: 0x 0 [MCU2_0] 17.825270 s: 0x6b: 0x 0 [MCU2_0] 17.825454 s: 0x6c: 0x 0 [MCU2_0] 17.825623 s: 0x6d: 0x 0 [MCU2_0] 17.825785 s: 0x6e: 0x20 [MCU2_0] 17.825945 s: 0x6f: 0x 0 [MCU2_0] 17.826105 s: 0x70: 0x80 [MCU2_0] 17.826341 s: 0x71: 0x 0 [MCU2_0] 17.826528 s: 0x72: 0x 0 [MCU2_0] 17.826696 s: 0x73: 0x 0 [MCU2_0] 17.826860 s: 0x74: 0x 0 [MCU2_0] 17.827023 s: 0x75: 0x 0 [MCU2_0] 17.827278 s: 0x76: 0x 0 [MCU2_0] 17.827468 s: 0x77: 0x24 [MCU2_0] 17.827638 s: 0x78: 0x 0 [MCU2_0] 17.827804 s: 0x79: 0x 0 [MCU2_0] 17.827968 s: 0x7a: 0x 0 [MCU2_0] 17.828130 s: 0x7b: 0x 0 [MCU2_0] 17.828412 s: 0x7c: 0x 0 [MCU2_0] 17.828598 s: 0x7d: 0x 0 [MCU2_0] 17.828767 s: 0x7e: 0x7f [MCU2_0] 17.828933 s: 0x7f: 0x 0 [MCU2_0] 17.829095 s: 0x80: 0x 0 [MCU2_0] 17.829341 s: 0x81: 0x 0 [MCU2_0] 17.829524 s: 0x82: 0x 0 [MCU2_0] 17.829694 s: 0x83: 0x 0 [MCU2_0] 17.829858 s: 0x84: 0x 0 [MCU2_0] 17.830018 s: 0x85: 0x 0 [MCU2_0] 17.830277 s: 0x86: 0x 0 [MCU2_0] 17.830466 s: 0x87: 0x 0 [MCU2_0] 17.830638 s: 0x88: 0x 0 [MCU2_0] 17.830803 s: 0x89: 0x 0 [MCU2_0] 17.830963 s: 0x8a: 0x 0 [MCU2_0] 17.831124 s: 0x8b: 0x 0 [MCU2_0] 17.831392 s: 0x8c: 0x 0 [MCU2_0] 17.831576 s: 0x8d: 0x 0 [MCU2_0] 17.831744 s: 0x8e: 0x 0 [MCU2_0] 17.831909 s: 0x8f: 0x 0 [MCU2_0] 17.832074 s: 0x90: 0x 0 [MCU2_0] 17.832351 s: 0x91: 0x 0 [MCU2_0] 17.832543 s: 0x92: 0x 0 [MCU2_0] 17.832718 s: 0x93: 0x 0 [MCU2_0] 17.832883 s: 0x94: 0x 0 [MCU2_0] 17.833050 s: 0x95: 0x 0 [MCU2_0] 17.833284 s: 0x96: 0x 0 [MCU2_0] 17.833476 s: 0x97: 0x 0 [MCU2_0] 17.833642 s: 0x98: 0x 0 [MCU2_0] 17.833806 s: 0x99: 0x 0 [MCU2_0] 17.833968 s: 0x9a: 0x 0 [MCU2_0] 17.834135 s: 0x9b: 0x 0 [MCU2_0] 17.834416 s: 0x9c: 0x 0 [MCU2_0] 17.834595 s: 0x9d: 0x 0 [MCU2_0] 17.834761 s: 0x9e: 0x 0 [MCU2_0] 17.834922 s: 0x9f: 0x 0 [MCU2_0] 17.835084 s: 0xa0: 0x 0 [MCU2_0] 17.835343 s: 0xa1: 0x 0 [MCU2_0] 17.835527 s: 0xa2: 0x 0 [MCU2_0] 17.835699 s: 0xa3: 0x 0 [MCU2_0] 17.835863 s: 0xa4: 0x 0 [MCU2_0] 17.836024 s: 0xa5: 0x 0 [MCU2_0] 17.836271 s: 0xa6: 0x 0 [MCU2_0] 17.836457 s: 0xa7: 0x 0 [MCU2_0] 17.836622 s: 0xa8: 0x 0 [MCU2_0] 17.836785 s: 0xa9: 0x 0 [MCU2_0] 17.836948 s: 0xaa: 0x 0 [MCU2_0] 17.837109 s: 0xab: 0x 0 [MCU2_0] 17.837339 s: 0xac: 0x 0 [MCU2_0] 17.837527 s: 0xad: 0x 0 [MCU2_0] 17.837694 s: 0xae: 0x 0 [MCU2_0] 17.837858 s: 0xaf: 0x 0 [MCU2_0] 17.838021 s: 0xb0: 0x 0 [MCU2_0] 17.838270 s: 0xb1: 0x 0 [MCU2_0] 17.838456 s: 0xb2: 0x 0 [MCU2_0] 17.838626 s: 0xb3: 0x 0 [MCU2_0] 17.838791 s: 0xb4: 0x 0 [MCU2_0] 17.838950 s: 0xb5: 0x 0 [MCU2_0] 17.839112 s: 0xb6: 0x 0 [MCU2_0] 17.839341 s: 0xb7: 0x 0 [MCU2_0] 17.839526 s: 0xb8: 0x 0 [MCU2_0] 17.839693 s: 0xb9: 0x 0 [MCU2_0] 17.839857 s: 0xba: 0x 0 [MCU2_0] 17.840023 s: 0xbb: 0x 0 [MCU2_0] 17.840271 s: 0xbc: 0x 0 [MCU2_0] 17.840456 s: 0xbd: 0x 0 [MCU2_0] 17.840624 s: 0xbe: 0x 0 [MCU2_0] 17.840787 s: 0xbf: 0x 0 [MCU2_0] 17.840948 s: 0xc0: 0x 0 [MCU2_0] 17.841108 s: 0xc1: 0x 0 [MCU2_0] 17.841332 s: 0xc2: 0x82 [MCU2_0] 17.841520 s: 0xc3: 0x 0 [MCU2_0] 17.841689 s: 0xc4: 0x38 [MCU2_0] 17.841854 s: 0xc5: 0x 0 [MCU2_0] 17.842015 s: 0xc6: 0x 0 [MCU2_0] 17.842291 s: 0xc7: 0x60 [MCU2_0] 17.842480 s: 0xc8: 0x40 [MCU2_0] 17.842658 s: 0xc9: 0x 0 [MCU2_0] 17.842824 s: 0xca: 0x 0 [MCU2_0] 17.842987 s: 0xcb: 0x 0 [MCU2_0] 17.843152 s: 0xcc: 0x 0 [MCU2_0] 17.843434 s: 0xcd: 0x 2 [MCU2_0] 17.843604 s: 0xce: 0xff [MCU2_0] 17.843767 s: 0xcf: 0x 0 [MCU2_0] 17.843929 s: 0xd0: 0x 0 [MCU2_0] 17.844093 s: 0xd1: 0x 0 [MCU2_0] 17.844341 s: 0xd2: 0x 0 [MCU2_0] 17.844525 s: 0xd3: 0x 0 [MCU2_0] 17.844693 s: 0xd4: 0x 0 [MCU2_0] 17.844855 s: 0xd5: 0x 0 [MCU2_0] 17.845016 s: 0xd6: 0x 0 [MCU2_0] 17.845271 s: 0xd7: 0x 0 [MCU2_0] 17.845462 s: 0xd8: 0x 0 [MCU2_0] 17.845634 s: 0xd9: 0x 0 [MCU2_0] 17.845802 s: 0xda: 0x 0 [MCU2_0] 17.845967 s: 0xdb: 0x 0 [MCU2_0] 17.846129 s: 0xdc: 0x 0 [MCU2_0] 17.846400 s: 0xdd: 0x 0 [MCU2_0] 17.846592 s: 0xde: 0x 0 [MCU2_0] 17.846763 s: 0xdf: 0x 0 [MCU2_0] 17.846928 s: 0xe0: 0x 0 [MCU2_0] 17.847092 s: 0xe1: 0x 0 [MCU2_0] 17.847357 s: 0xe2: 0x82 [MCU2_0] 17.847548 s: 0xe3: 0x 0 [MCU2_0] 17.847717 s: 0xe4: 0x28 [MCU2_0] 17.847880 s: 0xe5: 0x 8 [MCU2_0] 17.848042 s: 0xe6: 0x 0 [MCU2_0] 17.848279 s: 0xe7: 0x 0 [MCU2_0] 17.848465 s: 0xe8: 0x 0 [MCU2_0] 17.848636 s: 0xe9: 0x 0 [MCU2_0] 17.848799 s: 0xea: 0x 0 [MCU2_0] 17.848960 s: 0xeb: 0x 0 [MCU2_0] 17.849124 s: 0xec: 0x 0 [MCU2_0] 17.849387 s: 0xed: 0x 2 [MCU2_0] 17.849574 s: 0xee: 0x 0 [MCU2_0] 17.849742 s: 0xef: 0x 0 [MCU2_0] 17.849908 s: 0xf0: 0x5f [MCU2_0] 17.850073 s: 0xf1: 0x55 [MCU2_0] 17.850343 s: 0xf2: 0x42 [MCU2_0] 17.850530 s: 0xf3: 0x39 [MCU2_0] 17.850697 s: 0xf4: 0x34 [MCU2_0] 17.850862 s: 0xf5: 0x31 [MCU2_0] 17.851024 s: 0xf6: 0x 0 [MCU2_0] 17.851276 s: 0xf7: 0x 0 [MCU2_0] 17.851458 s: 0xf8: 0x 0 [MCU2_0] 17.851627 s: 0xf9: 0x 0 [MCU2_0] 17.851791 s: 0xfa: 0x 0 [MCU2_0] 17.851955 s: 0xfb: 0x 0 [MCU2_0] 17.852117 s: 0xfc: 0x 0 [MCU2_0] 17.852338 s: 0xfd: 0x 0 [MCU2_0] 17.852522 s: 0xfe: 0x 0 [MCU2_0] 17.852691 s: 0xff: 0x 0 [MCU2_0] 17.852726 s: dump ub941 registers done [MCU2_0] 17.852763 s: DSS: SERDES Configuration... Done !!! [MCU2_0] 17.856428 s: DSS: Init ... Done !!! [MCU2_0] 17.856498 s: VHWA: VPAC Init ... !!! [MCU2_0] 17.856530 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2 [MCU2_0] 17.856747 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 17.856788 s: VHWA: LDC Init ... !!! [MCU2_0] 17.860491 s: VHWA: LDC Init ... Done !!! [MCU2_0] 17.860562 s: VHWA: MSC Init ... !!! [MCU2_0] 17.872716 s: VHWA: MSC Init ... Done !!! [MCU2_0] 17.872787 s: VHWA: NF Init ... !!! [MCU2_0] 17.874938 s: VHWA: NF Init ... Done !!! [MCU2_0] 17.875009 s: VHWA: VISS Init ... !!! [MCU2_0] 17.886581 s: VHWA: VISS Init ... Done !!! [MCU2_0] 17.886653 s: VHWA: VPAC Init ... Done !!! [MCU2_0] 17.886700 s: VX_ZONE_INIT:Enabled [MCU2_0] 17.886731 s: VX_ZONE_ERROR:Enabled [MCU2_0] 17.886758 s: VX_ZONE_WARNING:Enabled [MCU2_0] 17.888127 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target IPU1-0 [MCU2_0] 17.888581 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target VPAC_NF [MCU2_0] 17.888827 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target VPAC_LDC1 [MCU2_0] 17.889049 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target VPAC_MSC1 [MCU2_0] 17.889496 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target VPAC_MSC2 [MCU2_0] 17.889813 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target VPAC_VISS1 [MCU2_0] 17.890089 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target CAPTURE1 [MCU2_0] 17.890504 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target CAPTURE2 [MCU2_0] 17.890791 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target DISPLAY1 [MCU2_0] 17.891074 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target DISPLAY2 [MCU2_0] 17.891481 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target CSITX [MCU2_0] 17.891799 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target CAPTURE3 [MCU2_0] 17.892088 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target CAPTURE4 [MCU2_0] 17.892538 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target CAPTURE5 [MCU2_0] 17.892856 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target CAPTURE6 [MCU2_0] 17.893305 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target CAPTURE7 [MCU2_0] 17.893656 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target CAPTURE8 [MCU2_0] 17.893931 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target DSS_M2M1 [MCU2_0] 17.894411 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target DSS_M2M2 [MCU2_0] 17.894706 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target DSS_M2M3 [MCU2_0] 17.894971 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target DSS_M2M4 [MCU2_0] 17.895031 s: VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!! [MCU2_0] 17.895069 s: APP: OpenVX Target kernel init ... !!! [MCU2_0] 17.916914 s: APP: OpenVX Target kernel init ... Done !!! [MCU2_0] 17.916989 s: CSI2RX: Init ... !!! [MCU2_0] 17.917019 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2 [MCU2_0] 17.917155 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 17.917367 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2 [MCU2_0] 17.917534 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 17.917577 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2 [MCU2_0] 17.917722 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 17.917758 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2 [MCU2_0] 17.917859 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 17.917897 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2 [MCU2_0] 17.917996 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 17.918935 s: CSI2RX: Init ... Done !!! [MCU2_0] 17.919007 s: ISS: Init ... !!! [MCU2_0] 17.919058 s: IssSensor_Init ... Done !!! [MCU2_0] 17.919363 s: vissRemoteServer_Init ... Done !!! [MCU2_0] 17.919455 s: IttRemoteServer_Init ... Done !!! [MCU2_0] 17.919497 s: UDMA Copy: Init ... !!! [MCU2_0] 17.921333 s: UDMA Copy: Init ... Done !!! [MCU2_0] 17.921441 s: APP: Init ... Done !!! [MCU2_0] 17.921482 s: APP: Run ... !!! [MCU2_0] 17.921511 s: IPC: Starting echo test ... [MCU2_1] 4.098940 s: CIO: Init ... Done !!! [MCU2_1] 4.099010 s: ### CPU Frequency = 1000000000 Hz [MCU2_1] 4.099053 s: APP: Init ... !!! [MCU2_1] 4.099078 s: SCICLIENT: Init ... !!! [MCU2_1] 4.099336 s: SCICLIENT: DMSC FW version [22.1.1--v2022.01 (Terrific Llam] [MCU2_1] 4.099385 s: SCICLIENT: DMSC FW revision 0x16 [MCU2_1] 4.099419 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU2_1] 4.099455 s: SCICLIENT: Init ... Done !!! [MCU2_1] 4.099497 s: UDMA: Init ... !!! [MCU2_1] 4.100904 s: UDMA: Init ... Done !!! [MCU2_1] 4.100968 s: MEM: Init ... !!! [MCU2_1] 4.101012 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ da000000 of size 16777216 bytes !!! [MCU2_1] 4.101085 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3640000 of size 262144 bytes !!! [MCU2_1] 4.101146 s: MEM: Init ... Done !!! [MCU2_1] 4.101170 s: IPC: Init ... !!! [MCU2_1] 4.101231 s: IPC: 6 CPUs participating in IPC !!! [MCU2_1] 4.101281 s: IPC: Waiting for HLOS to be ready ... !!! [MCU2_1] 17.387335 s: IPC: HLOS is ready !!! [MCU2_1] 17.402701 s: IPC: Init ... Done !!! [MCU2_1] 17.402768 s: APP: Syncing with 5 CPUs ... !!! [MCU2_1] 17.439387 s: APP: Syncing with 5 CPUs ... Done !!! [MCU2_1] 17.439593 s: REMOTE_SERVICE: Init ... !!! [MCU2_1] 17.441253 s: REMOTE_SERVICE: Init ... Done !!! [MCU2_1] 17.441317 s: FVID2: Init ... !!! [MCU2_1] 17.441391 s: FVID2: Init ... Done !!! [MCU2_1] 17.441425 s: VHWA: DMPAC: Init ... !!! [MCU2_1] 17.441451 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2 [MCU2_1] 17.441985 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 17.442025 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2 [MCU2_1] 17.442486 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 17.442519 s: VHWA: DOF Init ... !!! [MCU2_1] 17.450606 s: VHWA: DOF Init ... Done !!! [MCU2_1] 17.450665 s: VHWA: SDE Init ... !!! [MCU2_1] 17.453179 s: VHWA: SDE Init ... Done !!! [MCU2_1] 17.453233 s: VHWA: DMPAC: Init ... Done !!! [MCU2_1] 17.453278 s: VX_ZONE_INIT:Enabled [MCU2_1] 17.453307 s: VX_ZONE_ERROR:Enabled [MCU2_1] 17.453333 s: VX_ZONE_WARNING:Enabled [MCU2_1] 17.454471 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target DMPAC_SDE [MCU2_1] 17.454730 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target DMPAC_DOF [MCU2_1] 17.454970 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:54] Added target IPU1-1 [MCU2_1] 17.455025 s: VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!! [MCU2_1] 17.455061 s: APP: OpenVX Target kernel init ... !!! [MCU2_1] 17.455361 s: APP: OpenVX Target kernel init ... Done !!! [MCU2_1] 17.455402 s: UDMA Copy: Init ... !!! [MCU2_1] 17.457262 s: UDMA Copy: Init ... Done !!! [MCU2_1] 17.457336 s: APP: Init ... Done !!! [MCU2_1] 17.457372 s: APP: Run ... !!! [MCU2_1] 17.457400 s: IPC: Starting echo test ... [MCU2_1] 17.460375 s: APP: Run ... Done !!! [MCU2_1] 17.461664 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[.] C7X_1[.] [MCU2_1] 17.461789 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[.] [MCU2_1] 17.461881 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P] [MCU2_1] 17.935847 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P] [C6x_1 ] 4.167604 s: CIO: Init ... Done !!! [C6x_1 ] 4.167629 s: ### CPU Frequency = 1350000000 Hz [C6x_1 ] 4.167640 s: APP: Init ... !!! [C6x_1 ] 4.167647 s: SCICLIENT: Init ... !!! [C6x_1 ] 4.167870 s: SCICLIENT: DMSC FW version [22.1.1--v2022.01 (Terrific Llam] [C6x_1 ] 4.167881 s: SCICLIENT: DMSC FW revision 0x16 [C6x_1 ] 4.167891 s: SCICLIENT: DMSC FW ABI revision 3.1 [C6x_1 ] 4.167900 s: SCICLIENT: Init ... Done !!! [C6x_1 ] 4.167909 s: UDMA: Init ... !!! [C6x_1 ] 4.169338 s: UDMA: Init ... Done !!! [C6x_1 ] 4.169355 s: MEM: Init ... !!! [C6x_1 ] 4.169368 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ dc000000 of size 16777216 bytes !!! [C6x_1 ] 4.169386 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!! [C6x_1 ] 4.169401 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ dd000000 of size 50331648 bytes !!! [C6x_1 ] 4.169417 s: MEM: Init ... Done !!! [C6x_1 ] 4.169425 s: IPC: Init ... !!! [C6x_1 ] 4.169446 s: IPC: 6 CPUs participating in IPC !!! [C6x_1 ] 4.169459 s: IPC: Waiting for HLOS to be ready ... !!! [C6x_1 ] 16.008799 s: IPC: HLOS is ready !!! [C6x_1 ] 16.012677 s: IPC: Init ... Done !!! [C6x_1 ] 16.012703 s: APP: Syncing with 5 CPUs ... !!! [C6x_1 ] 17.439374 s: APP: Syncing with 5 CPUs ... Done !!! [C6x_1 ] 17.439388 s: REMOTE_SERVICE: Init ... !!! [C6x_1 ] 17.440017 s: REMOTE_SERVICE: Init ... Done !!! [C6x_1 ] 17.440055 s: VX_ZONE_INIT:Enabled [C6x_1 ] 17.440066 s: VX_ZONE_ERROR:Enabled [C6x_1 ] 17.440076 s: VX_ZONE_WARNING:Enabled [C6x_1 ] 17.440791 s: VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!! [C6x_1 ] 17.440857 s: APP: OpenVX Target kernel init ... !!! [C6x_1 ] 17.441181 s: APP: OpenVX Target kernel init ... Done !!! [C6x_1 ] 17.441200 s: UDMA Copy: Init ... !!! [C6x_1 ] 17.444661 s: UDMA Copy: Init ... Done !!! [C6x_1 ] 17.444680 s: APP: Init ... Done !!! [C6x_1 ] 17.445477 s: APP: Run ... !!! [C6x_1 ] 17.445487 s: IPC: Starting echo test ... [C6x_1 ] 17.446550 s: APP: Run ... Done !!! [C6x_1 ] 17.446869 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[s] C66X_2[x] C7X_1[P] [C6x_1 ] 17.447043 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_1 ] 17.460973 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_1 ] 17.935697 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_2 ] 4.261215 s: CIO: Init ... Done !!! [C6x_2 ] 4.261241 s: ### CPU Frequency = 1350000000 Hz [C6x_2 ] 4.261252 s: APP: Init ... !!! [C6x_2 ] 4.261260 s: SCICLIENT: Init ... !!! [C6x_2 ] 4.261481 s: SCICLIENT: DMSC FW version [22.1.1--v2022.01 (Terrific Llam] [C6x_2 ] 4.261493 s: SCICLIENT: DMSC FW revision 0x16 [C6x_2 ] 4.261503 s: SCICLIENT: DMSC FW ABI revision 3.1 [C6x_2 ] 4.261513 s: SCICLIENT: Init ... Done !!! [C6x_2 ] 4.261522 s: UDMA: Init ... !!! [C6x_2 ] 4.262969 s: UDMA: Init ... Done !!! [C6x_2 ] 4.262986 s: MEM: Init ... !!! [C6x_2 ] 4.263000 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e0000000 of size 16777216 bytes !!! [C6x_2 ] 4.263018 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!! [C6x_2 ] 4.263033 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e1000000 of size 50331648 bytes !!! [C6x_2 ] 4.263049 s: MEM: Init ... Done !!! [C6x_2 ] 4.263058 s: IPC: Init ... !!! [C6x_2 ] 4.263079 s: IPC: 6 CPUs participating in IPC !!! [C6x_2 ] 4.263092 s: IPC: Waiting for HLOS to be ready ... !!! [C6x_2 ] 16.675861 s: IPC: HLOS is ready !!! [C6x_2 ] 16.679546 s: IPC: Init ... Done !!! [C6x_2 ] 16.679574 s: APP: Syncing with 5 CPUs ... !!! [C6x_2 ] 17.439374 s: APP: Syncing with 5 CPUs ... Done !!! [C6x_2 ] 17.439388 s: REMOTE_SERVICE: Init ... !!! [C6x_2 ] 17.440029 s: REMOTE_SERVICE: Init ... Done !!! [C6x_2 ] 17.440069 s: VX_ZONE_INIT:Enabled [C6x_2 ] 17.440080 s: VX_ZONE_ERROR:Enabled [C6x_2 ] 17.440089 s: VX_ZONE_WARNING:Enabled [C6x_2 ] 17.440852 s: VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!! [C6x_2 ] 17.440871 s: APP: OpenVX Target kernel init ... !!! [C6x_2 ] 17.441192 s: APP: OpenVX Target kernel init ... Done !!! [C6x_2 ] 17.441211 s: UDMA Copy: Init ... !!! [C6x_2 ] 17.444797 s: UDMA Copy: Init ... Done !!! [C6x_2 ] 17.444816 s: APP: Init ... Done !!! [C6x_2 ] 17.445584 s: APP: Run ... !!! [C6x_2 ] 17.445594 s: IPC: Starting echo test ... [C6x_2 ] 17.446740 s: APP: Run ... Done !!! [C6x_2 ] 17.447047 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[.] C66X_2[s] C7X_1[P] [C6x_2 ] 17.447082 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[s] C7X_1[P] [C6x_2 ] 17.461007 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P] [C6x_2 ] 17.935747 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P] [C7x_1 ] 4.494031 s: CIO: Init ... Done !!! [C7x_1 ] 4.494046 s: ### CPU Frequency = 1000000000 Hz [C7x_1 ] 4.494057 s: APP: Init ... !!! [C7x_1 ] 4.494064 s: SCICLIENT: Init ... !!! [C7x_1 ] 4.494276 s: SCICLIENT: DMSC FW version [22.1.1--v2022.01 (Terrific Llam] [C7x_1 ] 4.494289 s: SCICLIENT: DMSC FW revision 0x16 [C7x_1 ] 4.494299 s: SCICLIENT: DMSC FW ABI revision 3.1 [C7x_1 ] 4.494310 s: SCICLIENT: Init ... Done !!! [C7x_1 ] 4.494319 s: UDMA: Init ... !!! [C7x_1 ] 4.495419 s: UDMA: Init ... Done !!! [C7x_1 ] 4.495431 s: MEM: Init ... !!! [C7x_1 ] 4.495442 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ 100000000 of size 268435456 bytes !!! [C7x_1 ] 4.495463 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!! [C7x_1 ] 4.495480 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 458752 bytes !!! [C7x_1 ] 4.495497 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!! [C7x_1 ] 4.495514 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e4000000 of size 385875968 bytes !!! [C7x_1 ] 4.495532 s: MEM: Init ... Done !!! [C7x_1 ] 4.495540 s: IPC: Init ... !!! [C7x_1 ] 4.495553 s: IPC: 6 CPUs participating in IPC !!! [C7x_1 ] 4.495567 s: IPC: Waiting for HLOS to be ready ... !!! [C7x_1 ] 17.437363 s: IPC: HLOS is ready !!! [C7x_1 ] 17.439345 s: IPC: Init ... Done !!! [C7x_1 ] 17.439360 s: APP: Syncing with 5 CPUs ... !!! [C7x_1 ] 17.439374 s: APP: Syncing with 5 CPUs ... Done !!! [C7x_1 ] 17.439384 s: REMOTE_SERVICE: Init ... !!! [C7x_1 ] 17.439531 s: REMOTE_SERVICE: Init ... Done !!! [C7x_1 ] 17.439554 s: VX_ZONE_INIT:Enabled [C7x_1 ] 17.439564 s: VX_ZONE_ERROR:Enabled [C7x_1 ] 17.439573 s: VX_ZONE_WARNING:Enabled [C7x_1 ] 17.439753 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1 [C7x_1 ] 17.439847 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_2 [C7x_1 ] 17.439947 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_3 [C7x_1 ] 17.440018 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_4 [C7x_1 ] 17.440085 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_5 [C7x_1 ] 17.440203 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_6 [C7x_1 ] 17.440272 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_7 [C7x_1 ] 17.440333 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_8 [C7x_1 ] 17.440354 s: VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!! [C7x_1 ] 17.440367 s: APP: OpenVX Target kernel init ... !!! [C7x_1 ] 17.440549 s: APP: OpenVX Target kernel init ... Done !!! [C7x_1 ] 17.440562 s: APP: Init ... Done !!! [C7x_1 ] 17.440571 s: APP: Run ... !!! [C7x_1 ] 17.440578 s: IPC: Starting echo test ... [C7x_1 ] 17.440731 s: APP: Run ... Done !!! [C7x_1 ] 17.446875 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[.] C7X_1[s] [C7x_1 ] 17.447043 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[P] C7X_1[s] [C7x_1 ] 17.461036 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s] [C7x_1 ] 17.935778 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s] root@j7-evm:/opt/vision_apps# ./run_app_dof.sh APP: Init ... !!! MEM: Init ... !!! MEM: Initialized DMA HEAP (fd=4) !!! MEM: Init ... Done !!! IPC: Init ... !!! IPC: Init ... Done !!! REMOTE_SERVICE: Init ... !!! REMOTE_SERVICE: Init ... Done !!! 381.268733 s: GTC Frequency = 200 MHz APP: Init ... Done !!! 381.275282 s: VX_ZONE_INIT:Enabled 381.275320 s: VX_ZONE_ERROR:Enabled 381.275325 s: VX_ZONE_WARNING:Enabled 381.277689 s: VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!! 381.279589 s: VX_ZONE_INIT:[tivxHostInitLocal:86] Initialization Done for HOST !!! ================================= Demo : Dense Optical Flow Example 1 ================================= p: Print performance statistics e: Export performance statistics x: Exit Enter Choice: 0x60: 0x22 ================================= Demo : Dense Optical Flow Example 1 ================================= p: Print performance statistics e: Export performance statistics x: Exit Enter Choice: ================================= Demo : Dense Optical Flow Example 1 ================================= p: Print performance statistics e: Export performance statistics x: Exit Enter Choice: 385.856847 s: VX_ZONE_INIT:[tivxHostDeInitLocal:100] De-Initialization Done for HOST !!! 385.861243 s: VX_ZONE_INIT:[tivxDeInitLocal:193] De-Initialization Done !!! APP: Deinit ... !!! REMOTE_SERVICE: Deinit ... !!! REMOTE_SERVICE: Deinit ... Done !!! IPC: Deinit ... !!! IPC: DeInit ... Done !!! MEM: Deinit ... !!! MEM: Alloc's: 34 alloc's of 34859676 bytes MEM: Free's : 34 free's of 34859676 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! APP: Deinit ... Done !!! root@j7-evm:/opt/vision_apps#
