AM6442: A problem about warm reset while booting from eMMC

Hi Charles,
You may check the two registers on reset sources
- CTRLMMR_RST_SRC Register @0x43018178
- CTRLMMR_MCU_RST_SRC Register @0x04518178
I'm attaching a sample log from POR, and then issuing "reset" @u-boot from eMMC boot on AM64x EVM for your reference.
Best,
-Hong

U-Boot SPL 2021.01-g44a87e3ab8 (Mar 30 2022 - 16:29:38 +0000)
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
SPL initial stack usage: 13392 bytes
Reading daughtercard EEPROM at 0x52 failed -1
Trying to boot from MMC1
init_env from device 9 not supported!
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.5(release):08.01.00.006-dirty
NOTICE:  BL31: Built : 16:24:35, Mar 30 2022

U-Boot SPL 2021.01-g44a87e3ab8 (Mar 30 2022 - 16:28:20 +0000)
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
Reading daughtercard EEPROM at 0x52 failed -1
Trying to boot from MMC1


U-Boot 2021.01-g44a87e3ab8 (Mar 30 2022 - 16:28:20 +0000)

SoC:   AM64X SR1.0
Model: Texas Instruments AM642 EVM
Board: AM64-GPEVM rev E2
DRAM:  2 GiB
NAND:  1024 MiB
MMC:   mmc@fa10000: 0, mmc@fa00000: 1
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
Reading daughtercard EEPROM at 0x52 failed -1
Net:   eth0: ethernet@8000000port@1
Hit any key to stop autoboot:  2  0 
=> md.l 0x43018178 1
43018178: 00000000                               ....
=> md.l 0x04518178 1
04518178: 00000000                               ....
=> reset
resetting ...

U-Boot SPL 2021.01-g44a87e3ab8 (Mar 30 2022 - 16:29:38 +0000)
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
SPL initial stack usage: 13392 bytes
Reading daughtercard EEPROM at 0x52 failed -1
Trying to boot from MMC1
init_env from device 9 not supported!
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.5(release):08.01.00.006-dirty
NOTICE:  BL31: Built : 16:24:35, Mar 30 2022

U-Boot SPL 2021.01-g44a87e3ab8 (Mar 30 2022 - 16:28:20 +0000)
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
Reading daughtercard EEPROM at 0x52 failed -1
Trying to boot from MMC1


U-Boot 2021.01-g44a87e3ab8 (Mar 30 2022 - 16:28:20 +0000)

SoC:   AM64X SR1.0
Model: Texas Instruments AM642 EVM
Board: AM64-GPEVM rev E2
DRAM:  2 GiB
NAND:  1024 MiB
MMC:   mmc@fa10000: 0, mmc@fa00000: 1
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
Reading daughtercard EEPROM at 0x52 failed -1
Net:   eth0: ethernet@8000000port@1
Hit any key to stop autoboot:  2  0 
=> md.l 0x43018178 1
43018178: 00200000                               .. .
=> md.l 0x04518178 1
04518178: 00200000                               .. .
=> 

Hi Hong Guan64,

Thanks for your reply.

According to your advice,we did some tests about this problem.

First,I tunned on the hardware booting from SD CARD.When I reseted the hareware by the RESET_REQz HW pin,
the system reboot and then checked the register providing by your replyed.I found the value of the register like the following picture.

Second,I tunned on the hardware booting from eMMC.When I reseted by the RESET_REQz HW pin,
the system did not reboot,I could only get the value of the register by connecting to the core of R5 via CCS,like the following picture.

At this time ,I could not connected to the core of A53 via CCS.

What should I do next?

Hi Charles,

I'm looping in my HW colleague to comment on RESET_REQz difference on SD and eMMC on your board.

Best,

-Hong

Hello Hiong, 

Thank you for looping.

Chares, would you be able to share the schematics for a quick review ?

If not, can you please compare the EVM and the custom board you have designed for reset implementation.

Regards,

Sreenivasa

Hi,

Here is the hardware designed for reset system,especially for the signal of RESET_REQz.

Hello Charles chen,

Thank you for the schematics. The issues is with the eMMc reset during warm rese.

Can you please make sure that the eMMC is reset during warm reset. Please refer the anding logic for eMMC reset in the EVM.

Regards,

Sreenivasa

Hi,Sreenivasa,

Thanks for your reply.

I have already checked that the eMMC has reseted during warm reset.

Here is the hardware designed for eMMC,especially for the connection between RESETSTAT and eMMC.

Can you help me to check the design?

Best,

Charles

Hello Charles, 

Thank you for the inputs. There is a 100K resistors (R121) and the reset is being controlled through the diode. Not sure if the device is seeing a defined reset level. 

Could you please measure the voltage at R121 terminal connected to the memory device during reset.

Regards,

Sreenivasa

Hi,Sreenivasa,

The voltage at R121 terminal connected to the eMMC device is 0.14V during warm reset.

Hello Charles, 

If i understand correctly, the eMMC interface works during power up and does not work during subsequent warm reset.

We are anding multiple reset sources in the EVM. With the above schematics, i am not able to understand the logic completely.

Can you please change the R121 to a lower value (10K ) and test.

Regards,

Sreenivasa

Hi,Sreenivasa

Yes,now the eMMC interface works during power up and does not work during subsequent warm reset.

I have alreaty change the R121 to 10K and test.But it doesn't solve the problem.

And I also change the design like the following picture.But it doesn't solve the problem.

Can you have another suggestion for this problem?

Best,

Charles

Hi,Sreenivasa

I also have a test on TMDS64GPEVM board like the following picture.

I found that the TMDS64GPEVM board can be reboot by push the SW6 button on board.

I think there is nothing to do with the reset design of eMMC circuit.

What do you think?

Best,

Charles

Hello Charles, 

Thank you for the inputs.

Reboot by push would be a validation of the logic but not confirmation that warm reset works.

Could you please use an anding logic to test the logic on your board.

The eMMC has requirements to be reset any time the SoC is reset.

Regards,

Sreenivasa

Hi,Sreenivasa,

Although the issue still not to be resolved,your suggestions is good for us.

Thanks a lot.