AM6442: EMMC Boot Meet Resetting Problem

Hi Kevin,

After DFU flashed the eMMC, did you warm-reset or power-cycle the board? Does the eMMC boot issue still happens after you power-cycled the board?

Does the board have JTAG connection so that you can use CCS to check registers?

Hi Bin,

After DFU flashed the eMMC, customer has tried multiple times power-cycle the board, but still will struck at the below position.

After it prints "resetting", it will not continue. May I know what could be this reason?

Many Thanks,

Kevin

Hi Bin,

Also at this time when it stuck, customer has tried connecting to ccs vis jtag, but jtag could not be connected.

Kevin

Hi Kevin,

Kevin Peng said:

After it prints "resetting", it will not continue. May I know what could be this reason?

This is the first time I heard about such issue, don't know what could cause the problem.

Kevin Peng said:

Also at this time when it stuck, customer has tried connecting to ccs vis jtag, but jtag could not be connected.

What is the connection failure? Please note that at this stage, A53_0 is not running yet, you cannot connect to A53_0, but you should be able to connect to the DAP core.

Hi Bin,

Thanks, customer will try to connect to DAP core tomorrow.

By the way, do you think this might due to some HW issues? I have attached the corresponding schematic above, it should be the same as EVM.

Thanks,

Kevin

Hi Kevin,

Kevin Peng said:

By the way, do you think this might due to some HW issues?

I am unable to tell at this moment.

Kevin Peng said:

customer will try to connect to DAP core tomorrow.

If it is possible to connect to DAP, please read the register 0x43018178.

Hi Kevin,

Please also ask the customer to test with SDK9.2 U-Boot to see if the same issue also happens.

0x43018178 is 0x0. 

Does your board have a PMIC? If so, when the U-Boot SPL does reset, does the PMIC turns off the power then turns it back on?

Please test with SDK9.2 U-Boot to see if the same issue also happens.

hi All,

I read out the ext csd and confirm that ext csd 162 RST_n_FUNCTION is set to 1.

It is not the eMMC ext csd problem. It seem the SoC power got turned off when U-Boot SPL does warm reset.

Hi Bin,

     But our board uses descrte dcdc and ldo, the power cannot controlled by cpu.

hi Bin,

        And another issue is that mmc report timeout after kernel boot and it cannot get systemd startup and obtain console.

the following is the log file. please help.

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 6.6.32-g6de6e418c80e-dirty (xxxx@xxxx-xxx-N000) (aarch64-oe-linux-gcc (GCC) 13.3.0, GNU ld (GNU Bin                                                                                        utils) 2.42.0.20240716) #2 SMP PREEMPT Fri Nov  1 00:40:09 CST 2024
[    0.000000] KASLR disabled due to lack of seed
[    0.000000] Machine model: Texas Instruments AM642 EVM
[    0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002800000 (options '')
[    0.000000] printk: bootconsole [ns16550a0] enabled
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created DMA memory pool at 0x0000000090000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@90000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x0000000090000000..0x00000000900fffff (1024 KiB) nomap non-reusable r5f-dma-memory@90000000
[    0.000000] Reserved memory: created DMA memory pool at 0x0000000090100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@90100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x0000000090100000..0x0000000090ffffff (15360 KiB) nomap non-reusable r5f-memory@90100000
[    0.000000] Reserved memory: created DMA memory pool at 0x0000000091000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@91000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x0000000091000000..0x00000000910fffff (1024 KiB) nomap non-reusable r5f-dma-memory@91000000
[    0.000000] Reserved memory: created DMA memory pool at 0x0000000091100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@91100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x0000000091100000..0x0000000091ffffff (15360 KiB) nomap non-reusable r5f-memory@91100000
[    0.000000] Reserved memory: created DMA memory pool at 0x0000000092000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@92000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x0000000092000000..0x00000000920fffff (1024 KiB) nomap non-reusable r5f-dma-memory@92000000
[    0.000000] Reserved memory: created DMA memory pool at 0x0000000092100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@92100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x0000000092100000..0x0000000092ffffff (15360 KiB) nomap non-reusable r5f-memory@92100000
[    0.000000] Reserved memory: created DMA memory pool at 0x0000000093000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@93000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x0000000093000000..0x00000000930fffff (1024 KiB) nomap non-reusable r5f-dma-memory@93000000
[    0.000000] Reserved memory: created DMA memory pool at 0x0000000093100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@93100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x0000000093100000..0x0000000093ffffff (15360 KiB) nomap non-reusable r5f-memory@93100000
[    0.000000] Reserved memory: created DMA memory pool at 0x0000000094000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node m4f-dma-memory@94000000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x0000000094000000..0x00000000940fffff (1024 KiB) nomap non-reusable m4f-dma-memory@94000000
[    0.000000] Reserved memory: created DMA memory pool at 0x0000000094100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node m4f-memory@94100000, compatible id shared-dma-pool
[    0.000000] OF: reserved mem: 0x0000000094100000..0x0000000094ffffff (15360 KiB) nomap non-reusable m4f-memory@94100000
[    0.000000] OF: reserved mem: 0x0000000095000000..0x00000000957fffff (8192 KiB) nomap non-reusable ipc-memories@95000000
[    0.000000] OF: reserved mem: 0x000000009e800000..0x000000009fffffff (24576 KiB) nomap non-reusable optee@9e800000
[    0.000000] Zone ranges:
[    0.000000]   DMA      [mem 0x0000000080000000-0x000000009fffffff]
[    0.000000]   DMA32    empty
[    0.000000]   Normal   empty
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000080000000-0x000000008fffffff]
[    0.000000]   node   0: [mem 0x0000000090000000-0x00000000957fffff]
[    0.000000]   node   0: [mem 0x0000000095800000-0x000000009e7fffff]
[    0.000000]   node   0: [mem 0x000000009e800000-0x000000009fffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fffffff]
[    0.000000] cma: Reserved 32 MiB at 0x000000009be00000 on node -1
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] psci: SMC Calling Convention v1.4
[    0.000000] percpu: Embedded 20 pages/cpu s42920 r8192 d30808 u81920
[    0.000000] Detected VIPT I-cache on CPU0
[    0.000000] CPU features: detected: GIC system register CPU interface
[    0.000000] CPU features: detected: ARM erratum 845719
[    0.000000] alternatives: applying boot alternatives
[    0.000000] Kernel command line: console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 omap2-nand.0:2m(NAND.tiboot3),2m(NAND.tispl),2m(NAND.t                                                                                        iboot3.backup),4m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup),-(NAND.file-system) root=PARTUUID=e14aea3b-1f60-447e-b0df-37a749a38                                                                                        7e9 rw rootfstype=ext4 rootwait
[    0.000000] Dentry cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
[    0.000000] Inode-cache hash table entries: 32768 (order: 6, 262144 bytes, linear)
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 129024
[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
[    0.000000] software IO TLB: area num 2.
[    0.000000] software IO TLB: mapped [mem 0x0000000097dc0000-0x000000009bdc0000] (64MB)
[    0.000000] Memory: 280032K/524288K available (11904K kernel code, 1214K rwdata, 3996K rodata, 2368K init, 502K bss, 211488K reserved, 32768K cma-                                                                                        reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] rcu:     RCU event tracing is enabled.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=2.
[    0.000000]  Trampoline variant of Tasks RCU enabled.
[    0.000000]  Tracing variant of Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[    0.000000] GICv3: 256 SPIs implemented
[    0.000000] GICv3: 0 Extended SPIs implemented
[    0.000000] Root IRQ handler: gic_handle_irq
[    0.000000] GICv3: GICv3 features: 16 PPIs
[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001840000
[    0.000000] ITS [mem 0x01820000-0x0182ffff]
[    0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS
[    0.000000] ITS@0x0000000001820000: Devices Table too large, reduce ids 20->19
[    0.000000] ITS@0x0000000001820000: allocated 524288 Devices @80800000 (flat, esz 8, psz 64K, shr 0)
[    0.000000] ITS: using cache flushing for cmd queue
[    0.000000] GICv3: using LPI property table @0x0000000080040000
[    0.000000] GIC: using cache flushing for LPI property table
[    0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000080050000
[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
[    0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0x3ffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns
[    0.000001] sched_clock: 58 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns
[    0.008641] Console: colour dummy device 80x25
[    0.013246] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000)
[    0.023925] pid_max: default: 32768 minimum: 301
[    0.028735] LSM: initializing lsm=capability,integrity
[    0.034113] Mount-cache hash table entries: 1024 (order: 1, 8192 bytes, linear)
[    0.041595] Mountpoint-cache hash table entries: 1024 (order: 1, 8192 bytes, linear)
[    0.051569] RCU Tasks: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1.
[    0.058921] RCU Tasks Trace: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1.
[    0.066901] rcu: Hierarchical SRCU implementation.
[    0.071812] rcu:     Max phase no-delay instances is 1000.
[    0.077472] Platform MSI: msi-controller@1820000 domain created
[    0.083848] PCI/MSI: /bus@f4000/interrupt-controller@1800000/msi-controller@1820000 domain created
[    0.093379] EFI services will not be available.
[    0.098350] smp: Bringing up secondary CPUs ...
I/TC: Secondary CPU 1 initializing
I/TC: Secondary CPU 1 switching to normal world boot
[    0.112019] Detected VIPT I-cache on CPU1
[    0.112123] GICv3: CPU1: found redistributor 1 region 0:0x0000000001860000
[    0.112143] GICv3: CPU1: using allocated LPI pending table @0x0000000080060000
[    0.112202] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[    0.112345] smp: Brought up 1 node, 2 CPUs
[    0.141731] SMP: Total of 2 processors activated.
[    0.146542] CPU features: detected: 32-bit EL0 Support
[    0.151814] CPU features: detected: CRC32 instructions
[    0.157133] CPU: All CPU(s) started at EL2
[    0.161319] alternatives: applying system-wide alternatives
[    0.168511] devtmpfs: initialized
[    0.181473] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.191487] futex hash table entries: 512 (order: 3, 32768 bytes, linear)
[    0.199873] pinctrl core: initialized pinctrl subsystem
[    0.205879] DMI not present or invalid.
[    0.210621] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[    0.217704] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
[    0.225104] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
[    0.233159] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[    0.241363] audit: initializing netlink subsys (disabled)
[    0.247181] audit: type=2000 audit(0.156:1): state=initialized audit_enabled=0 res=1
[    0.247755] thermal_sys: Registered thermal governor 'step_wise'
[    0.255132] thermal_sys: Registered thermal governor 'power_allocator'
[    0.261534] cpuidle: using governor menu
[    0.272474] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.279482] ASID allocator initialised with 65536 entries
[    0.296859] platform a40000.pinctrl: Fixed dependency cycle(s) with /bus@f4000/pinctrl@a40000/cpsw-cpts-pps
[    0.310827] Modules: 27712 pages in range for non-PLT usage
[    0.310848] Modules: 519232 pages in range for PLT usage
[    0.317656] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
[    0.330093] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
[    0.336500] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
[    0.343435] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
[    0.349840] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
[    0.356776] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
[    0.363187] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
[    0.370123] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
[    0.378409] k3-chipinfo 43000014.chipid: Family:AM64X rev:SR2.0 JTAGID[0x1bb3802f] Detected
[    0.388080] iommu: Default domain type: Translated
[    0.393028] iommu: DMA domain TLB invalidation policy: strict mode
[    0.399731] SCSI subsystem initialized
[    0.404113] usbcore: registered new interface driver usbfs
[    0.409780] usbcore: registered new interface driver hub
[    0.415249] usbcore: registered new device driver usb
[    0.420960] pps_core: LinuxPPS API ver. 1 registered
[    0.426043] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.435388] PTP clock support registered
[    0.439592] EDAC MC: Ver: 3.0.0
[    0.443674] scmi_core: SCMI protocol bus registered
[    0.449169] FPGA manager framework
[    0.452815] Advanced Linux Sound Architecture Driver Initialized.
[    0.460220] vgaarb: loaded
[    0.463498] clocksource: Switched to clocksource arch_sys_counter
[    0.470071] VFS: Disk quotas dquot_6.6.0
[    0.474126] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    0.489024] NET: Registered PF_INET protocol family
[    0.494244] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
[    0.502439] tcp_listen_portaddr_hash hash table entries: 256 (order: 0, 4096 bytes, linear)
[    0.511077] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[    0.519017] TCP established hash table entries: 4096 (order: 3, 32768 bytes, linear)
[    0.526978] TCP bind hash table entries: 4096 (order: 5, 131072 bytes, linear)
[    0.534497] TCP: Hash tables configured (established 4096 bind 4096)
[    0.541130] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
[    0.547831] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
[    0.555128] NET: Registered PF_UNIX/PF_LOCAL protocol family
[    0.561520] RPC: Registered named UNIX socket transport module.
[    0.567627] RPC: Registered udp transport module.
[    0.572437] RPC: Registered tcp transport module.
[    0.577244] RPC: Registered tcp-with-tls transport module.
[    0.582850] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.589458] NET: Registered PF_XDP protocol family
[    0.594377] PCI: CLS 0 bytes, default 64
[    0.599918] Initialise system trusted keyrings
[    0.604815] workingset: timestamp_bits=46 max_order=17 bucket_order=0
[    0.611897] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.618322] NFS: Registering the id_resolver key type
[    0.623567] Key type id_resolver registered
[    0.627845] Key type id_legacy registered
[    0.631967] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    0.638820] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[    0.686967] Key type asymmetric registered
[    0.691171] Asymmetric key parser 'x509' registered
[    0.696228] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 244)
[    0.703791] io scheduler mq-deadline registered
[    0.708445] io scheduler kyber registered
[    0.712591] io scheduler bfq registered
[    0.719646] pinctrl-single 4084000.pinctrl: 33 pins, size 132
[    0.726137] pinctrl-single f4000.pinctrl: 180 pins, size 720
[    0.733622] pinctrl-single a40000.pinctrl: 512 pins, size 2048
[    0.746993] Serial: 8250/16550 driver, 12 ports, IRQ sharing enabled
[    0.766357] loop: module loaded
[    0.770885] megasas: 07.725.01.00-rc1
[    0.777540] tun: Universal TUN/TAP device driver, 1.6
[    0.784173] VFIO - User Level meta-driver version: 0.3
[    0.790739] usbcore: registered new interface driver usb-storage
[    0.797363] i2c_dev: i2c /dev entries driver
[    0.803054] sdhci: Secure Digital Host Controller Interface driver
[    0.809418] sdhci: Copyright(c) Pierre Ossman
[    0.814159] sdhci-pltfm: SDHCI platform and OF driver helper
[    0.820735] ledtrig-cpu: registered to indicate activity on CPUs
[    0.827272] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[    0.834748] usbcore: registered new interface driver usbhid
[    0.840460] usbhid: USB HID core driver
[    0.844816] omap-mailbox 29020000.mailbox: omap mailbox rev 0x66fc9100
[    0.851784] omap-mailbox 29040000.mailbox: omap mailbox rev 0x66fc9100
[    0.858653] omap-mailbox 29060000.mailbox: omap mailbox rev 0x66fc9100
[    0.867176] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
[    0.876342] optee: probing for conduit method.
I/TC: Reserved shared memory is enabled
I/TC: Dynamic shared memory is enabled
I/TC: Normal World virtualization support is disabled
I/TC: Asynchronous notifications are disabled
[    0.880934] optee: revision 4.2 (12d7c4ee)
[    0.897612] optee: dynamic shared memory is enabled
[    0.907815] random: crng init done
[    0.911459] optee: initialized driver
[    0.917804] NET: Registered PF_PACKET protocol family
[    0.923127] Key type dns_resolver registered
[    0.936980] registered taskstats version 1
[    0.941553] Loading compiled-in X.509 certificates
[    0.961510] ti-sci 44043000.system-controller: ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
[    1.073465] ti-sci-clk 44043000.system-controller:clock-controller: recalc-rate failed for dev=62, clk=3, ret=-19
[    1.112190] ti-sci-intr bus@f4000:interrupt-controller@a00000: Interrupt Router 3 domain created
[    1.121626] ti-sci-inta 48000000.interrupt-controller: Interrupt Aggregator domain 28 created
[    1.130747] ti-udma 485c0100.dma-controller: Number of rings: 68
[    1.138616] ti-udma 485c0100.dma-controller: Channels: 24 (bchan: 12, tchan: 6, rchan: 6)
[    1.148958] ti-udma 485c0000.dma-controller: Number of rings: 288
[    1.166608] ti-udma 485c0000.dma-controller: Channels: 44 (tchan: 29, rchan: 15)
[    1.178019] printk: console [ttyS2] disabled
[    1.183086] 2800000.serial: ttyS2 at MMIO 0x2800000 (irq = 315, base_baud = 3000000) is a 8250
[    1.192029] printk: console [ttyS2] enabled
[    1.192029] printk: console [ttyS2] enabled
[    1.200491] printk: bootconsole [ns16550a0] disabled
[    1.200491] printk: bootconsole [ns16550a0] disabled
[    1.215618] spi-nor spi0.0: unrecognized JEDEC id bytes: 90 80 2f 90 80 2f
[    1.224040] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.267506] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.277838] davinci_mdio 8000f00.mdio: phy[7]: device 8000f00.mdio:07, driver TI DP83826C
[    1.286102] am65-cpsw-nuss 8000000.ethernet: initializing am65 cpsw nuss version 0x6BA00903, cpsw version 0x6BA80903 Ports: 3 quirks:00000006
[    1.298934] am65-cpsw-nuss 8000000.ethernet: initialized cpsw ale version 1.4
[    1.306067] am65-cpsw-nuss 8000000.ethernet: ALE Table size 512
[    1.312780] pps pps0: new PPS source ptp0
[    1.317230] am65-cpsw-nuss 8000000.ethernet: CPTS ver 0x4e8a010c, freq:500000000, add_val:1 pps:1
[    1.334640] am65-cpsw-nuss 8000000.ethernet: set new flow-id-base 16
[    1.346878] am65-cpts 39000000.cpts: CPTS ver 0x4e8a010c, freq:500000000, add_val:1 pps:0
[    1.357137] mmc0: CQHCI version 5.10
[    1.370279] clk: Disabling unused clocks
[    1.380208] ti-sci-clk 44043000.system-controller:clock-controller: is_prepared failed for dev=62, clk=3, ret=-19
[    1.402162] mmc0: SDHCI controller on fa10000.mmc [fa10000.mmc] using ADMA 64-bit
[    1.411236] ALSA device list:
[    1.414308]   No soundcards found.
[    1.418278] Waiting for root device PARTUUID=e14aea3b-1f60-447e-b0df-37a749a387e9...
[    1.488701] mmc0: Command Queue Engine enabled
[    1.493220] mmc0: new HS200 MMC card at address 0001
[    1.499032] mmcblk0: mmc0:0001 M04A11 3.64 GiB
[    1.508261]  mmcblk0: p1
[    1.511646] mmcblk0boot0: mmc0:0001 M04A11 4.00 MiB
[    1.517879] mmcblk0boot1: mmc0:0001 M04A11 4.00 MiB
[    1.524097] mmcblk0rpmb: mmc0:0001 M04A11 4.00 MiB, chardev (239:0)
[    1.542402] EXT4-fs (mmcblk0p1): recovery complete
[    1.547278] EXT4-fs (mmcblk0p1): mounted filesystem bef90e4d-4ff1-4f75-a999-38b6040d4747 r/w with ordered data mode. Quota mode: none.
[    1.559434] VFS: Mounted root (ext4 filesystem) on device 179:1.
[    1.567555] devtmpfs: mounted
[    1.572300] Freeing unused kernel memory: 2368K
[    1.576959] Run /sbin/init as init process



[   62.587579] mmc0: cqhci: timeout for tag 2, qcnt 4
[   62.592411] mmc0: cqhci: ============ CQHCI REGISTER DUMP ===========
[   62.598847] mmc0: cqhci: Caps:      0x000030c8 | Version:  0x00000510
[   62.605282] mmc0: cqhci: Config:    0x00000101 | Control:  0x00000000
[   62.611716] mmc0: cqhci: Int stat:  0x00000000 | Int enab: 0x00000016
[   62.618150] mmc0: cqhci: Int sig:   0x00000016 | Int Coal: 0x00000000
[   62.624585] mmc0: cqhci: TDL base:  0x8142a000 | TDL up32: 0x00000000
[   62.631019] mmc0: cqhci: Doorbell:  0x0008001c | TCN:      0x00000000
[   62.637452] mmc0: cqhci: Dev queue: 0x00000040 | Dev Pend: 0x0008001c
[   62.643886] mmc0: cqhci: Task clr:  0x00000000 | SSC1:     0x00011000
[   62.650324] mmc0: cqhci: SSC2:      0x00000001 | DCMD rsp: 0x00000000
[   62.656758] mmc0: cqhci: RED mask:  0xfdf9a080 | TERRI:    0x00000000
[   62.663192] mmc0: cqhci: Resp idx:  0x0000002d | Resp arg: 0x00000900
[   62.669626] mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
[   62.676058] mmc0: sdhci: Sys addr:  0x00000090 | Version:  0x00001004
[   62.682491] mmc0: sdhci: Blk size:  0x00000200 | Blk cnt:  0x00000000
[   62.688925] mmc0: sdhci: Argument:  0x00000282 | Trn mode: 0x00000033
[   62.695358] mmc0: sdhci: Present:   0x01ff00f0 | Host ctl: 0x0000003c
[   62.701791] mmc0: sdhci: Power:     0x0000000b | Blk gap:  0x00000080
[   62.708229] mmc0: sdhci: Wake-up:   0x00000000 | Clock:    0x00000007
[   62.714662] mmc0: sdhci: Timeout:   0x0000000e | Int stat: 0x00000000
[   62.721095] mmc0: sdhci: Int enab:  0x02ff4000 | Sig enab: 0x02ff4000
[   62.727528] mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000
[   62.733961] mmc0: sdhci: Caps:      0x7cecc801 | Caps_1:   0x98002407
[   62.740394] mmc0: sdhci: Cmd:       0x00002d1a | Max curr: 0x00000000
[   62.746828] mmc0: sdhci: Resp[0]:   0x00000900 | Resp[1]:  0xfff6dbff
[   62.753262] mmc0: sdhci: Resp[2]:   0x329f5903 | Resp[3]:  0x00d02701
[   62.759695] mmc0: sdhci: Host ctl2: 0x00000003
[   62.764135] mmc0: sdhci: ADMA Err:  0x00000000 | ADMA Ptr: 0x000000009bf80618
[   62.771266] mmc0: sdhci: ============================================
[   62.777724] mmc0: running CQE recovery
[  124.027575] mmc0: cqhci: timeout for tag 16, qcnt 1
[  124.032494] mmc0: cqhci: ============ CQHCI REGISTER DUMP ===========
[  124.038929] mmc0: cqhci: Caps:      0x000030c8 | Version:  0x00000510
[  124.045364] mmc0: cqhci: Config:    0x00000101 | Control:  0x00000000
[  124.051798] mmc0: cqhci: Int stat:  0x00000000 | Int enab: 0x00000016
[  124.058232] mmc0: cqhci: Int sig:   0x00000016 | Int Coal: 0x00000000
[  124.064667] mmc0: cqhci: TDL base:  0x8142a000 | TDL up32: 0x00000000
[  124.071100] mmc0: cqhci: Doorbell:  0x00010000 | TCN:      0x00000000
[  124.077534] mmc0: cqhci: Dev queue: 0x00400000 | Dev Pend: 0x00010000
[  124.083967] mmc0: cqhci: Task clr:  0x00000000 | SSC1:     0x00011000
[  124.090405] mmc0: cqhci: SSC2:      0x00000001 | DCMD rsp: 0x00000000
[  124.096839] mmc0: cqhci: RED mask:  0xfdf9a080 | TERRI:    0x00000000
[  124.103273] mmc0: cqhci: Resp idx:  0x0000002e | Resp arg: 0x00000900
[  124.109707] mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
[  124.116139] mmc0: sdhci: Sys addr:  0x00000028 | Version:  0x00001004
[  124.122572] mmc0: sdhci: Blk size:  0x00000200 | Blk cnt:  0x00000000
[  124.129005] mmc0: sdhci: Argument:  0x00170000 | Trn mode: 0x00000033
[  124.135438] mmc0: sdhci: Present:   0x01ff00f0 | Host ctl: 0x0000003c
[  124.141872] mmc0: sdhci: Power:     0x0000000b | Blk gap:  0x00000080
[  124.148310] mmc0: sdhci: Wake-up:   0x00000000 | Clock:    0x00000007
[  124.154744] mmc0: sdhci: Timeout:   0x0000000e | Int stat: 0x00000000
[  124.161177] mmc0: sdhci: Int enab:  0x02ff4000 | Sig enab: 0x02ff4000
[  124.167610] mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000
[  124.174043] mmc0: sdhci: Caps:      0x7cecc801 | Caps_1:   0x98002407
[  124.180477] mmc0: sdhci: Cmd:       0x00002e3a | Max curr: 0x00000000
[  124.186910] mmc0: sdhci: Resp[0]:   0x00000900 | Resp[1]:  0xfff6dbff
[  124.193344] mmc0: sdhci: Resp[2]:   0x329f5903 | Resp[3]:  0x00d02701
[  124.199777] mmc0: sdhci: Host ctl2: 0x00000003
[  124.204216] mmc0: sdhci: ADMA Err:  0x00000000 | ADMA Ptr: 0x000000009bf88a24
[  124.211347] mmc0: sdhci: ============================================
[  124.217802] mmc0: running CQE recovery

Hi Bin,

To explain more clearly, customer just tried removing the code for workaround ErrataID i2331 in the Uboot, now they could warm reset successfully.

However, the mmc report timeout after kernel boot and it cannot get systemd startup, customer has provided the corresponding log above, please help have a look.

Many Thanks,

Kevin

hi Bin,

I comment out workaround Errata Code in the u-boot and now the board can warm reset without stuck.

I'm not clear what's the root cause. I'll verify.

Hi Wangbin,

The Errata code shouldn't be removed. To continue on finding its root cause, please

- With the Errata code, when SPL triggers the warm reset, please probe all the power rails to see if there are still in the valid range during the reset;

- test with SDK9.2 U-boot, to see if the reset loop issue also happens.

Kevin,

Kevin Peng said:

However, the mmc report timeout after kernel boot and it cannot get systemd startup

This should be a separate issue, not relevant to the warm reset loop problem. Please help create a separate e2e thread for the eMMC timeout issue and assign the thread to me and I will help understand the problem. It is not a good idea to work two irrelevant issues in this single thread.

Hi Wangbin,

wangbin215 said:

I comment out workaround Errata Code in the u-boot and now the board can warm reset without stuck.

When the Errata code removed, and you manually did reset command in U-Boot prompt, and the system rebooted and U-Boot ran again.

At this time, please stop at U-Boot prompt, and run the following command to dump the register 0x43018178 and let me know its value:

=> md.l 0x43018178 1

Hi Bin,

Thanks for your suggestion, I have created a separate E2E to discuss the timeout issue, many thanks!

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1432664/am6442-emmc-timeout-in-booting-kernel

Kevin

Hi Bin,

When the Errata code removed, and after warm rest, 0x43018178 reads out 0x10000.

However, after add the errata code back, the soft reset will get stuck again.

Hi Bin,

Since this is on the customer board and has some modifications, so it is not easy for customer to directly test on SDK9.2, they need some porting efforts.

Thanks,

Kevin

Hi Wangbin,

Please do the following tests.

1. Apply the following U-Boot patch to SDK10.0. It prints the rst_src register value before and after the reset.

diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index 80c3cb3479f7..e539885ef9ec 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -231,6 +231,7 @@ void board_init_f(ulong dummy)
                printf("\n%s:uclass device error [%d]\n",__func__,ret);
 
        rst_src = readl(CTRLMMR_MCU_RST_SRC);
+       printf("rst_src: 0x%x\n", rst_src);
        if (rst_src == COLD_BOOT || rst_src & (SW_POR_MCU | SW_POR_MAIN)) {
                printf("Resetting on cold boot to workaround ErrataID:i2331\n");
                printf("Please resend tiboot3.bin in case of UART/DFU boot\n");

2. If the register value is always '0' after reset, please probe all the power rails to see if there are still in the valid range during the reset.

Kevin Peng said:

Since this is on the customer board and has some modifications, so it is not easy for customer to directly test on SDK9.2, they need some porting efforts.

3. You don't have to port the entire SDK9.2. Please just copy over the SYSFW binaries from the SDK9.2 to SDK10.0 and rebuild the SDK10.0 U-Boot. Following show the process that I did.

dev@ula:~$ cd sdk/am64x-plsdk-10074/board-support/prebuilt-images/am64xx-evm/
dev@ula:am64xx-evm$ mv ti-sysfw ti-sysfw.orig
dev@ula:am64xx-evm$ cp -r ~/sdk/am64x-plsdk-9.2.1.a/board-support/prebuilt-images/am64xx-evm/ti-sysfw ti-sysfw.sdk92
dev@ula:am64xx-evm$ ln -s ti-sysfw.sdk92 ti-sysfw
dev@ula:am64xx-evm$ ls -ld ti-sysfw*
lrwxrwxrwx 1 lb lb   13 Nov  1 10:29 ti-sysfw -> ti-sysfw.sdk92
drwxr-xr-x 2 lb lb 4096 Aug  5 05:41 ti-sysfw.orig
drwxr-xr-x 2 lb lb 4096 Nov  1 10:20 ti-sysfw.sdk92
dev@ula:am64xx-evm$ cd ../..
dev@ula:board-support$ rm -rf u-boot-build/
dev@ula:board-support$ cd ..
dev@ula:am64x-plsdk-10074$ make u-boot

Hi Bin & Kevin,

        I follow your suggestion but still get warm reset stuck during tiboot3.

I tested with 9.02 sysfw, the result is same.

It just prints out rst_src:0 because it gets stuck there.

I measure the RESETSTATz signal with oscilloscope.

This warm reset signal cannot be triggered during errata work around do_reset code.

But if remove the code and issue the reset command in a53 u-boot, the RESETSTATz signal can be triggered.

So the reason for rst_src remaining 0 is not the power dropped but the cpu is not performed a warm reset.

It is possible to move the errata work around warm reset code to a53 u-boot from the r5 tiboot3?

Hi Wangbin,

wangbin215 said:

It just prints out rst_src:0 because it gets stuck there.

This is strange. I see 0x10000 in my test on AM64x EVM with SDK10.0 u-boot. Did you modify the U-Boot defconfig when compiling U-Boot?

wangbin215 said:

It is possible to move the errata work around warm reset code to a53 u-boot from the r5 tiboot3?

If this errata workaround was removed, the system could lockup later when you want to use Ethernet in Linux.

Can you please try to replace the do_reset code in U-Boot with the line below?

writel(6, CTRLMMR_MCU_RST_CTRL);

Yes. I modified the defconfig and did a little modification for source code.

The main differrences between EVM and our customer board are:

1) DDR：we use 512MB DDR4 and DDR works without problem in this AM6442 project currently.

2) No eeprom. we removed eeprom chip. But EVM has an eeprom for board id. so i removed some code in uboot.

3) EMMC: we use 4GB MX52LM04A11XSI which is compitible with emmc 5.1. But It has default 4MB boot partition. So i changed defconfig and mmc dfu address to redefine the tiboot3, spl, uboot partition offset and size.

Hi Bin,

writel(6, CTRLMMR_MCU_RST_CTRL);

this doesn't work either.

Hi Bin,

Thanks for your reply.

With the Errata workaround code enabled, customer has measured the oscilloscope, and they found that there is warm reset signal at RESETSTATz, which means that it is stuck after receiving the warm reset signal. However, if they removed the Errata workaround code, and using the reset command after entering the A53, then it will not stuck anymore. Hence, customer wants to know if they could do it like this way (using the reset command after entering the A53)?

If not, we may need to figure out why the warm reset will stuck, is there any requirements that need the peripherals work together?

Please see the full log below.

U-Boot SPL 2024.04-00001-gd7c2ebb6-dirty (Nov 04 2024 - 23:41:19 +0800)
3
   - 2 'serial@2800000'
   - not found
0
   - 0 'sysctrler'
   - found
size=30, ptr=15b0, limit=80000: 7011cd80
rproc_pre_probe: 'sysctrler': using fdt
ofnode_read_prop: remoteproc-name: <not found>
ofnode_read_bool: remoteproc-internal-memory-mapped: false
clk_set_defaults(sysctrler)
clk_set_default_parents: could not read assigned-clock-parents for 7011cb0c
ofnode_read_prop: assigned-clock-rates: <not found>
k3_sysctrler_probe(dev=7011cb0c)
mbox_get_by_name(dev=7011cb0c, name=tx, chan=7011cd80)
mbox_get_by_index(dev=7011cb0c, index=0, chan=7011cd80)
fdtdec_get_int: #mbox-cells: x (1)
Looking for mailbox@4d000000
Looking for mailbox@4d000000
   - result for mailbox@4d000000: mailbox@4d000000 (ret=0)
   - result for mailbox@4d000000: mailbox@4d000000 (ret=0)
size=20, ptr=15d0, limit=80000: 7011cdb0
clk_set_defaults(bus@48000000)
clk_set_default_parents: could not read assigned-clock-parents for 7011baf8
ofnode_read_prop: assigned-clock-rates: <not found>
clk_set_defaults(mailbox@4d000000)
clk_set_default_parents: could not read assigned-clock-parents for 7011bb6c
ofnode_read_prop: assigned-clock-rates: <not found>
k3_sec_proxy_probe(dev=7011bb6c)
OF: ** translation for device mailbox@4d000000 **
OF: bus is default (na=2, ns=2) on bus@48000000
OF: translating address: 00000000 0000004d
OF: parent bus is default (na=2, ns=2) on bus@f4000
OF: walking ranges...
OF: default map, cp=x, s=x, da=x
OF: parent translation for: 00000000 00000048
OF: with offset: u
OF: one level translation: 00000000 0000004d
OF: parent bus is default (na=2, ns=2) on
OF: walking ranges...
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: parent translation for: 00000000 00000048
OF: with offset: u
OF: one level translation: 00000000 0000004d
OF: reached root node
OF: ** translation for device mailbox@4d000000 **
OF: bus is default (na=2, ns=2) on bus@48000000
OF: translating address: 00000000 0000404a
OF: parent bus is default (na=2, ns=2) on bus@f4000
OF: walking ranges...
OF: default map, cp=x, s=x, da=x
OF: parent translation for: 00000000 00000048
OF: with offset: u
OF: one level translation: 00000000 0000404a
OF: parent bus is default (na=2, ns=2) on
OF: walking ranges...
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: parent translation for: 00000000 00000048
OF: with offset: u
OF: one level translation: 00000000 0000404a
OF: reached root node
OF: ** translation for device mailbox@4d000000 **
OF: bus is default (na=2, ns=2) on bus@48000000
OF: translating address: 00000000 0000604a
OF: parent bus is default (na=2, ns=2) on bus@f4000
OF: walking ranges...
OF: default map, cp=x, s=x, da=x
OF: parent translation for: 00000000 00000048
OF: with offset: u
OF: one level translation: 00000000 0000604a
OF: parent bus is default (na=2, ns=2) on
OF: walking ranges...
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: parent translation for: 00000000 00000048
OF: with offset: u
OF: one level translation: 00000000 0000604a
OF: reached root node
size=154, ptr=1724, limit=80000: 7011cdd0
size=3c, ptr=1760, limit=80000: 7011cf24
size=3c, ptr=179c, limit=80000: 7011cf60
size=3c, ptr=17d8, limit=80000: 7011cf9c
size=3c, ptr=1814, limit=80000: 7011cfd8
size=3c, ptr=1850, limit=80000: 7011d014
size=3c, ptr=188c, limit=80000: 7011d050
size=3c, ptr=18c8, limit=80000: 7011d08c
size=3c, ptr=1904, limit=80000: 7011d0c8
size=3c, ptr=1940, limit=80000: 7011d104
size=3c, ptr=197c, limit=80000: 7011d140
size=3c, ptr=19b8, limit=80000: 7011d17c
size=3c, ptr=19f4, limit=80000: 7011d1b8
size=3c, ptr=1a30, limit=80000: 7011d1f4
size=3c, ptr=1a6c, limit=80000: 7011d230
size=3c, ptr=1aa8, limit=80000: 7011d26c
size=3c, ptr=1ae4, limit=80000: 7011d2a8
size=3c, ptr=1b20, limit=80000: 7011d2e4
k3_sec_proxy_of_xlate(chan=7011cd80)
k3_sec_proxy_request(chan=7011cd80)
mbox_get_by_name(dev=7011cb0c, name=rx, chan=7011cd8c)
mbox_get_by_index(dev=7011cb0c, index=1, chan=7011cd8c)
fdtdec_get_int: #mbox-cells: x (1)
fdtdec_get_int: #mbox-cells: x (1)
Looking for mailbox@4d000000
Looking for mailbox@4d000000
   - result for mailbox@4d000000: mailbox@4d000000 (ret=0)
   - result for mailbox@4d000000: mailbox@4d000000 (ret=0)
k3_sec_proxy_of_xlate(chan=7011cd8c)
k3_sec_proxy_request(chan=7011cd8c)
mbox_get_by_name(dev=7011cb0c, name=boot_notify, chan=7011cd98)
fdt_stringlist_search() failed: -61
k3_system_controller sysctrler: k3_of_to_priv: Acquiring optional Boot_notify failed. ret = -61. Using Rx
0
   - 0 'sysctrler'
   - found
_rproc_ops_wrapper: Starting sysctrler...
k3_sysctrler_start(dev=7011cb0c)
mbox_recv(chan=7011cd8c, data=7011b630, timeout_us=800000)
ofnode_read_prop: tick-timer: Looking for timer@2400000
Looking for timer@2400000
   - result for timer@2400000: timer@2400000 (ret=0)
   - result for timer@2400000: timer@2400000 (ret=0)
size=4, ptr=1b24, limit=80000: 7011d320
size=4, ptr=1b28, limit=80000: 7011d324
OF: ** translation for device timer@2400000 **
OF: bus is default (na=2, ns=2) on bus@f4000
OF: translating address: 00000000 00004002
OF: parent bus is default (na=2, ns=2) on
OF: walking ranges...
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: parent translation for: 00000000 00000001
OF: with offset: u
OF: one level translation: 00000000 00004002
OF: reached root node
clk_get_by_index_tail: Node 'timer@2400000', property 'clocks', failed to request CLK index 0: -2
ofnode_read_u32_index: clock-frequency: x (200000000)
clk_set_defaults(timer@2400000)
clk_set_default_parents: could not read assigned-clock-parents for 7011c21c
ofnode_read_prop: assigned-clock-rates: <not found>
k3_sec_proxy_recv(chan=7011cd8c, data=7011b630)
k3_sec_proxy_recv: Message successfully received from thread 0
k3_sysctrler_boot_notification_response: Boot notification received
k3_sysctrler_start: Boot notification received successfully on dev sysctrler
size=13c, ptr=1c64, limit=80000: 7011d328
clk_set_defaults(system-controller@44043000)
clk_set_default_parents: could not read assigned-clock-parents for 7011bc3c
ofnode_read_prop: assigned-clock-rates: <not found>
ti_sci_probe(dev=7011bc3c)
mbox_get_by_name(dev=7011bc3c, name=tx, chan=7011d420)
mbox_get_by_index(dev=7011bc3c, index=1, chan=7011d420)
fdtdec_get_int: #mbox-cells: x (1)
fdtdec_get_int: #mbox-cells: x (1)
Looking for mailbox@4d000000
Looking for mailbox@4d000000
   - result for mailbox@4d000000: mailbox@4d000000 (ret=0)
   - result for mailbox@4d000000: mailbox@4d000000 (ret=0)
k3_sec_proxy_of_xlate(chan=7011d420)
k3_sec_proxy_request(chan=7011d420)
mbox_get_by_name(dev=7011bc3c, name=rx, chan=7011d42c)
mbox_get_by_index(dev=7011bc3c, index=0, chan=7011d42c)
fdtdec_get_int: #mbox-cells: x (1)
Looking for mailbox@4d000000
Looking for mailbox@4d000000
   - result for mailbox@4d000000: mailbox@4d000000 (ret=0)
   - result for mailbox@4d000000: mailbox@4d000000 (ret=0)
k3_sec_proxy_of_xlate(chan=7011d42c)
k3_sec_proxy_request(chan=7011d42c)
mbox_get_by_name(dev=7011bc3c, name=notify, chan=7011d438)
mbox_get_by_index(dev=7011bc3c, index=2, chan=7011d438)
fdtdec_get_int: #mbox-cells: x (1)
fdtdec_get_int: #mbox-cells: x (1)
fdtdec_get_int: #mbox-cells: x (1)
Looking for mailbox@4d000000
Looking for mailbox@4d000000
   - result for mailbox@4d000000: mailbox@4d000000 (ret=0)
   - result for mailbox@4d000000: mailbox@4d000000 (ret=0)
k3_sec_proxy_of_xlate(chan=7011d438)
k3_sec_proxy_request(chan=7011d438)
ofnode_read_u32_index: ti,host-id: x (35)
ofnode_read_bool: ti,secure-host: true
size=18, ptr=1c7c, limit=80000: 7011d464
size=50, ptr=1ccc, limit=80000: 7011d47c
rst_src: 0x0
Resetting on cold boot to workaround ErrataID:i2331
Please resend tiboot3.bin in case of UART/DFU boot
resetting ...
size=4, ptr=1cd0, limit=80000: 7011d4cc
ti_sci_sysreset_probe(dev=7011d47c)
mbox_send(chan=7011d420, data=7011d444)
k3_sec_proxy_send(chan=7011d420, data=7011d444)
k3_sec_proxy_send: Message successfully sent on thread 1
mbox_recv(chan=7011d42c, data=7011d444, timeout_us=10000000)
k3_sec_proxy_recv(chan=7011d42c, data=7011d444)
k3_sec_proxy_recv: Message successfully received from thread 0
ti_sci_sysreset_request(dev=7011d47c, type=1)
mbox_send(chan=7011d420, data=7011d444)
k3_sec_proxy_send(chan=7011d420, data=7011d444)

Customer has tracked the "k3_sec_proxy_send" where they stuck seeing from the log. They use the CCS to track it below (based on SDK10.0).

We could see that after R5f called k3_sec_proxy_send and sent the reset request, the R5f will jump to ROM 0x418019F, and stuck in the loop inside the ROM. We do not understand the reason, maybe this could provide some clue for you to better understand this situation.

Many Thanks,

Kevin

Hi Bin,

Customer just tried one useful experiment. They put the same tiboot3.bin file which will stuck on their board to the EVM board, and they found that this tiboot3.bin file could boot normally in Uboot on the EVM. Hence, we suspect this may due to the HW differences. Is there any specific requirements on the peripherals that need the warm-reset work normally?

For example, there is an GPIO expander chip of I2C on the EVM, and the eMMC reset has logic device that has AND gate relationship with the GPIO expander. Customer board does not have this part. Does the K3 & ROM will read/write the GPIO expander of the I2C?

Thanks,

Kevin

Hi Wengbin,

wangbin215 said:

Yes. I modified the defconfig and did a little modification for source code.

Please attach the patch of your modification.

wangbin215 said:

writel(6, CTRLMMR_MCU_RST_CTRL);

this doesn't work either.

Do you mean tiboot3.bin still prints that rst_src register is still '0' after resetting?

Please describe the rst_src register value in all your description. Something like "doesn't work" or "got stuck" doesn't really help me understand the behavior.

Kevin,

Kevin Peng said:

Hence, we suspect this may due to the HW differences. Is there any specific requirements on the peripherals that need the warm-reset work normally?

I don't know yet. The warm reset in tiboot3.bin is all about the AM64x device, it shouldn't rely on any other external components, except the power rails. (By the way, I asked the customer to probe all the power rails during the warm reset to ensure they are in the valid voltage rage, but the customer has not clearly answered the question.)

Please email me the custom board schematics, I want to check if it will give any hint.

Kevin Peng said:

However, if they removed the Errata workaround code, and using the reset command after entering the A53, then it will not stuck anymore. Hence, customer wants to know if they could do it like this way (using the reset command after entering the A53)?

Yes, doing reset in A53 U-Boot is okay as long as Ethernet is not used in U-Boot and CPSW is disabled in U-Boot devicetree, it just increase a few seconds in the boot time.

Hi Kevin,

Kevin Peng said:

With the Errata workaround code enabled, customer has measured the oscilloscope, and they found that there is warm reset signal at RESETSTATz, which means that it is stuck after receiving the warm reset signal. However, if they removed the Errata workaround code, and using the reset command after entering the A53, then it will not stuck anymore. Hence, customer wants to know if they could do it like this way (using the reset command after entering the A53)?

If not, we may need to figure out why the warm reset will stuck, is there any requirements that need the peripherals work together?

I read your message again, it seems the behavior is changed now from the original report?

Now you say there IS RESETSTATz signal, but Wangbin said earlier that this signal wasn't triggered after i2331 reset in tiboot3.bin.

Now it seem ROM got stuck after the i2331 reset in tiboot3.bin, but originally the issue was that it is infinite loop between ROM and tiboot3.bin.

Is my understanding correct? What has changed which causes this different behavior?

Hi Bin&Kevin,

          I'll send the schematic and uboot patch to Kevin by mail today. Kevin, please kindly forward to Bin.

Let me do some summary:

1) It gets cpu stuck during tiboot3 errata work around warm reset on our custom board. Since it gets stuck, CTRLMMR_MCU_RST_SRC value only prints out once 0x0.

2) I measured the RESETSTATz warm reset signal. It has a active low pulse and same as evm.

3) JTAG show R5 CPU PC jumps to 0x418019F0 after K3 proxy send reset request. and it seems cpu loops at 0x418019F0. And 0x43018178 reads out 0x0.

4) If run the same binay directly on EVM, there's no stuck. warm reset is ok.

5) Remove  errata work around warm reset code and run on our custom board,  issue reset command in a53 u-boot works ok. CPU can successfully warm reset and then get CTRLMMR_MCU_RST_SRC value prints 0x10000.

Wangbin,

wangbin215 said:

1) It gets cpu stuck during tiboot3 errata work around warm reset on our custom board. Since it gets stuck, CTRLMMR_MCU_RST_SRC value only prints out once 0x0.

In Kevin's first post above last week, the issue is that the tiboot3 reset runs in an infinite loop, the execution does not go to tispl.bin. But now you say the tiboot3 reset causes it gets stuck in ROM. These are two completely different behaviors. Did you make any change which causes the behavior changed? any sw change, hw change or different board?

Hi Bin,

         Sorry，the problem description may not be very accurate in Kevin's first post.

The picture shows several repeated logs which are caused by manually cold reset. Since the CPU gets stuck after is shows "reseting....", I perform cold reset.

Actually, it get stuck in ROM.

Hi Bin,

       I move the errata work around warm reset code to a53 u-boot and it works.

It can successfully do warm reset.

But I'm not clear why spl cannot warm reset.

Wow, I completely misunderstood the problem...

Okay thanks for the clarification.

When you used DFU to flash eMMC, you have to transfer tiboot3.bin twice because of the i2331 reset, and this reset works fine in DFU boot, right?

So this problem does seem to be related to eMMC reset.

Please use a scope to capture the RESETSTATz signal close to eMMC device in both eMMC boot and DFU boot to see if the waveform are similar?

Hi Bin,

Yes. For DFU，both EVM and custom board needs transfer twice tiboot3, and this reset works fine.

I measured the RESETSTATz  signal yesterday in normal emmc boot mode instead of DFU mode. The warm reset pulses timing are almost same on customer board and EVM.

But the EMMC chip are not same.

Let me check the reset timing on datasheet later. 

Hi Wangbin,

I don't see any resister on RESETSTATz signal on AM64x EVM, so you might also try to remove R513 on your RESETSTATz line to see if it makes any difference.

Hi Bin，

I have already removed R513. It doesn't help.

the DS shows tRSCA need 200us, 74 cycles of clock signal are required before issuing CMD1 or CMD0 with argument 0xFFFFFFFA.

I don't know if the ROM code or hardware can meet this requirement.

But in a53 uboot, warm reset can work successfully. Is there any difference for warm reset booting?

Can you measure the RESETSTATz in tiboot3 and u-boot to see if there is any difference?

Yes, I'll measure it later.

Hi Bin，

I have measured the signal waveform. And there's difference.

This waveform is the warm reset invoked by a53 u-boot. It can warm reset successfully.

Once RESETSTATz asserted, it follows a lot of burst clocks.

And the following waveform is the errata work around warm reset in tiboot3. There's burst clocks after cold reset but none after warm reset.

It gets stuck at rom.

Hi Wangbin,

Can you please adjust the scales of the waveforms? I cannot really tell the details of the RESETSTATz signal in the two captures.

By the way, our hardware expert has provided comments to Kevin on your board design related to the reset. Did you modify the board according to the comments? Are these waveforms captured with or without the modifications?

The second waveform seems showing the eMMC device doesn't get reset. So please zoom in on the RESETSTATz signal to see if it has any difference in both cases, and if its signal quality meets the requirement in the AM64x datasheet.

Hi Bin,

I will let customer adjust the scales of the waveforms.

As for the HW modification, please refer to my latest email reply, customer has tried modified all of them, but the result is the same, maybe we need check if there is anything else need to modify.

Many Thanks,

Kevin

Thanks Kevin for supporting the customer. The issue now is more towards the hardware design related. Once we have clear waveforms, I might hand over this issue to our hardware expert to support, as I only support software.

hi Bin,

I have already changed the hardware according to Kevin's feedback. But it doesn't help.

I forgot  if the waveforms captured with or without the modifications. I think i can capture it again later.

The following is yesterday's RESTATz waveform.

reset pulse width is about 172us. And its width is same in both tiboot3 and a53 warm reset.

For tiboot3 warm reset, i cannot see the clk switched frequently in the waveform. But in a53 wam reset or cold reset, there's burst clk switching. It seems the rom warm reset behavior is inconsistent.

I noticed that thers's reset timing in the MXIC emmc datasheet. It requires 200us 74clks before issuing cmd. I've posted the timing in previous post.

So i'm not sure if the emmc reset is successful but the reset pulse width can meet the requirement.

Hi Wangbin,

Now it seems the waveform zooms in too much, I don't see the RESETSTATz signal toggling to show the reset.

Anyway, this is beyond my support scope, I am routing your query to our hardware expert. I summarize the issue here so that he doesn't have to go through this entire thread.

This is about eMMC boot/reset issue. When the custom AM64x board is powered on, due to i2331, at the beginning of the 2nd bootloader (R5 SPL) warmreset is issued, then ROM got stuck seems because the eMMC device is not reset properly and ROM cannot read the 2nd bootloader.

However, if the 2nd bootloader is modified to move the warmreset assertion from R5 SPL stage to the end (A53 U-Boot), right before booting Linux kernel, the eMMC device will be reset properly and the boot process is normal.

Hi Sreenivasa / Bin,

Please help review the HW schematic of EMMC reset part in my email and see if there is any modifications needed, thanks!

Customer also mentioned that there is 74 clocks requirement from the EMMC customer used, could you also help if our ROM could support it, as customer doubt if this could has some relationship with the problem as well.

Many Thanks,

Kevin

Hi Kevin,

I checked with the ROM team, the only eMMC command set to the eMMC device is CMD0 with argument of 0xFFFFFFFA to read the tiboot3.bin image, so the requirements you referred in the JEDEC Standard doesn't apply.

Please ask the customer do run a test, remove R513 so that the eMMC RSTn pin is disconnected with AM64x RESETSTATz pin, also remove the do_reset() in U-Boot SPL. Once power on the board and booted to U-Boot prompt, please do "reset" command to trigger warmreset, then see if the warmreset still get stuck in ROM or it can boot U-boot from eMMC.

hi Bin,

I have captured the waveform again. Successful warm reset and stucked warm reset have no obviouse difference.

CH1(yellow) is RESETSTATz

CH2(blue) is MMC_CLK

CH3(pink) is MMC_CMD

Successful warm reset waveforms:

Stucked warm reset waveforms:

Hi Bin, 

Once I  remove R513, warm reset will get stuck in a53 u-boot after type reset command.