AM625: DMSS Ring Accelerator Mapping

Grant Griffin

Part Number: AM625

The text below is from SPRUIV7 – MAY 2022. Please provide the missing table of ring Accelerator mapping indicated below, or confirm that the mapping ranges do not apply to the AM625

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11.2.1.3.1.1 DMSS Interrupt Description

This section describes the interrupt-related information that flows within DMSS and how this information is
configured or generated.
1. Ring Number (R#)
• Data is read from and written to a specific Ring Accelerator ring using direct ring-mode, or secure proxy
access
• The Ring Accelerator has specific ring number ranges for specific purposes. The R# must match
the intended purpose of the ring (see Table 10-578, RINGACC Ring Mapping) <Section under
development: no ring mapping section in spec, need to confirm if it exists in a different place
or just discard this sentence>

over 3 years ago

0 Rajashri Hazarika over 3 years ago

TI__Intellectual 1515 points

Hello,

Thanks for the query.

I will look into it and update you.

Regards

Rajashri

0 Kallikuppa Sreenivasa over 3 years ago in reply to Rajashri Hazarika

TI__Guru**** 169264 points

Hello Grat Griffin,

Please refer below the ring mapping

For bcdma the ring mapping is:

Chan type	Ring map	AM62
Block Copy (tx/rx pair)	0:(block copy channel count-1)	0:31
TX	Block copy channel count : (block copy channel count + tx channel count -1)	32:53
RX	(Block copy channel count + tx channel count ) : (block copy channel count + tx channel count + rx channel count -1)	54:75

Please le me know if there is any additional information that you are looking for..

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 169264 points

Hello Grat Griffin,

I have not heard from you and closing the thread.

Regards,

Sreenivasa

0 Grant Griffin over 3 years ago in reply to Kallikuppa Sreenivasa

Prodigy 90 points

I have since queried the DMASS0_BCDMA_0_CAP2 register which yielded the following count values: block copy count = 32, tx channel count = 22, rx channel count = 28. In the notation above, that implies the numbering of 0:31, 32:59, and 60:81, respectively.

Please help me reconcile the difference between your information and mine. I am inclined to use what the device actually reports, and assume there is some error in the table above. Do you agree?

0 Grant Griffin over 3 years ago in reply to Grant Griffin

Prodigy 90 points

Also, the reset values listed in Table 11-278 for the CAP2 register are each larger than the corresponding bit field can contain, and are inconsistent with both your information above and mine. Please provide the correct reset values.

0 Kallikuppa Sreenivasa over 3 years ago in reply to Grant Griffin

TI__Guru**** 169264 points

Hello Grat Griffin,

Thank you for the inputs. Let me review the inputs internally and update you.

Regards,

Sreenivasa

+1 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 169264 points

Hello Grat Griffin,

Thank you for the inputs on the TRM error and the channel counts.

Please refer below. We will work on making the required updates to the TRM.

Chan type	Ring map	AM62	AM62
Block Copy (tx/rx pair)	0:(block copy channel count-1)	0:31	0:(32-1) 0:31
TX	Block copy channel count : (block copy channel count + tx channel count -1)	32:53	(32):(32+22-1) 32:53
RX	(Block copy channel count + tx channel count ) : (block copy channel count + tx channel count + rx channel count -1)	54:75	(32+22):(32+22+28-1) 54:81

CAP2 (Capabilities Register 2), (0x28)

The Capabilities Register 2 specifies how many resources this BCDMA instance supports.

Bit	Name	Type	Reset	Description
31:27	reserved	r	0x0	Reserved
26:18	rchan_cnt	r	0x1c	Rx split channel count
17:9	tchan_cnt	r	0x16	Tx split channel count
8:0	chan_cnt	r	0x20	BC channel count

Regards,

Sreenivasa

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AM625: DMSS Ring Accelerator Mapping

CAP2 (Capabilities Register 2), (0x28)