AM625: DMSS QMODE Field Definition

The QMODE fields of the DMSS ring size registers are not fully defined in SPRUIV7 – MAY 2022:

• Table 11-125 describes the 3-bit QMODE field of the DMASS0_PKTDMA_0_RING_SIZE_J registers as "Defines the mode for this ring or queue. 1 | DRING_MODE | exposed
  ring mode with dual queues (forward/reverse) for SW direct access".
• Table 11-458 describes the 2-bit QMODE field of the MASS0_RINGACC_0_RING_SIZE_J registers as "Defines the mode for this ring or queue. 2 | CREDENTIALS_MODE | credentials mode is message mode plus stores credentials with each message, requiring the ring size to be doubled to fit the credentialsalong with the same number of elements when using the first 2 modes. Any exposed memory should be protected by a firewall from unwanted access. 1 | MESSAGE_MODE | messaging mode when all operations are through bus accesses, allowing multiple producers or consumers."

Additionally, the terms "DRING_MODE" and "CREDENTIALS_MODE" are not explicitly defined. (Do those maybe correspond to "11.2.2.2.2.1.1 Ring Mode" and "11.2.2.2.2.1.3 Credentials Mode", respectively?)

Please provide definitions for all possible QMODE bit values in both ring size register types, and provide explicit definitions for all valid queue modes.