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AM625: OLDI IO_CTRL register field definitions

Grant Griffin
Prodigy 90 points

Part Number: AM625

The fields of the OLDI IO_CTRL registers are not fully defined in the TRM, SPRUIV7 - May 2022. For example, bits 16-19 of OLDI0_CLK_IO_CTRL are described only as "Controls LVDS Transmitter TXDRV". Also, the reset value for that is listed as "64h" but it is only a 4-bit field. (The leading '6' appears to be incorrect.)

Please provide complete definitions for all fields of all OLDI IO_CTRL register. Also, please indicate whether the reset values listed in the SPRUIV7 result in OLDI (LVDS) signals being enabled by default on the corresponding AM62x pins, assuming that their pin muxes have been configured correctly.

  • 0
    TI__Guru**** 224565 points

    Hello Grant Griffin,

    Thank you for the inputs.

    Let me review your inputs and update you.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 224565 points

    Hello Grant Griffin,

    Thank you for the inputs. I understand the  bits 16-19 of OLDI0_CLK_IO_CTRL default value updates that you have suggested.

    Regarding the other question 

    Please provide complete definitions for all fields of all OLDI IO_CTRL register. 

    Can you please provide some additional details on the expected information.

    Regards,

    Sreenivasa

    . 

  • 0 in reply to Kallikuppa Sreenivasa
    Prodigy 90 points

    I require details of each bit value of each field of the register. Specifically, for single-bit fields, what does a '0' and a '1' do in that field? For multi-bit fields, what does each bit combination do.

    For example, for bits 16-19, there are 16 possible bit combinations. What does each possible combination do? The description of "Controls LVDS Transmitter TXDRV" is unsatisfactory because it is vague (what does "controls" actually mean here?) and in what specific way does each of the 16 possible values control the register?

    Please note that the same issue apples to other OLDI0_CLK_IO_CTRL fields, so I am only using bits 16-19 as an example. In order to make the AM62x DSS usable by me and your other customers, all fields of all of its registers will need to be fully described, as is commonly done in TRMs from other vendors.

  • 0 in reply to Grant Griffin
    TI__Guru**** 224565 points

    Hello Grant Griffin,

    Thank you for the inputs. 

    Let me check internally and update with any additional information i may have.

    Please expect delay in response as i look for the information.

    If there is any specific register of interest, i can check if that information can be prioritized.

    Regards,

    Sreenivasa

  • +1 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 224565 points

    Hello Grant Griffin,

    I am closing the thread summarizing the received inputs as below

    These CLK/DAT IO are not needed / intended to be used.

    Only two MMRs are needed:

      OLDI_PD_CTRL  the bandgap and power for the IO bias are off by default (for low power reasons) and need to be turned on in this register.

    • Padcfg  - picking the pin function as OLDI versus some other LVCMOS function will flip the LVDS/LVCMOS cell into LVDS mode

    Regards,

    Sreenivasa