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Original question:

TDA4VM: R5F Compare block Error forcing mode

TDA4VM: CCM error

Zhihua Ding
Intellectual 460 points
Part Number: TDA4VM

Hi，

I met a problem when develop the R5F CPU compare block in error forcing mode.

I can't get the register CCMSR.CMPE1 to be set when enter the error forcing mode. Is that because of campare block is disable?

Then, how can I get the error status when enter error focing mode? And where can I found the CPU_BUS_CMP_INT?

Last,  does below sentence mean I can only get the error status in one clock time?

 

BTW, we are not use the SDL directly, and we have check the code in SDL and can't find the detail information. 
If you can give more explaination about that.

Thank you and Best Regards,

Zhihua

  • 0
    TI__Guru** 120221 points

    Hi Zhihua,

    There is some SDL documentation on CCM is included in the release at SDL_RLS_01.00.00/sdl/sdl_docs/userguide/j721e/modules/r5fccm.html.   Recommendation is to refer to SDL examples where possible

    The PDK also contains CCM code, which is similar to SDL.

    • packages/ti/csl/diag/sdr/test/sdtf-test/src/sdtf_ccm.c
    • packages/ti/csl/csl/arch/r5/src/csl_mcu_armss_ccmr5.c
    • packages/ti/csl/csl/test/ccmr5/ccmr5_test_app/

    The below TRM statement in 6.3.3.5.1.6 Error Forcing Mode, indicates that the CMPE1 will be set.    The SDL example code does appear to be checking the CMPE1

    Regarding error status, user should expect to receive the error signal from CCMR5 once error forcing mode is entered.

    Regards,

    kb