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Original question:

AM625: IPC Mechanisms

AM625: Shared memory for IPC communication

AJITHKUMAR VIJAYAN
Intellectual 850 points
Part Number: AM625

Hello ,

1. Is it possible to use the MSRAM for the IPC shared memory ?

2. Which part of memory is advisable for the IPC Shared memory configuration ?

Currently there is no mention about the MSRAM in the AM62 TRM. On a different ticket, it was mentioned " There are other PSRAMs throughout the chip for use by other cores, but the 64K psram at base address 0x7000_0000 should be the equivalent to the 2MB msram on AM64 at base address 0x7000_0000. " 

3. Does that mean MSRAM is 2MB in size ?

  • 0
    TI__Guru** 101170 points

    Hello,

    Apologies for the confusion here.

    MSRAM Hardware Details

    To clarify:
    AM62x has 64kB of SRAM at base address 0x7000_0000. In the AM62x TRM Rev. 1.0, it looks like this memory is called "PSRAMECC_16K0_RAM" in the memory map. There are some references to "PSRAMECC_16k" later in the TRM. I assume this means "PSRAMECC_16K0_RAM" instead of "PSRAMECC_16K0_ECC_AGGR", but maybe it means both? Will need input from the HW application engineer.

    I am not sure why this memory has 16k in the name if it is 64kB. I am asking the HW folks for more input.

    Which part of memory to use for IPC? 

    What is your usecase for IPC? i.e., how much data are you needing to move? (throughput) Are there latency requirements? etc.

    You can find more information about designing a multicore usecase with IPC that needs to occur within a set cycle time, please reference https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1085663/faq-sitara-multicore-system-design-how-to-ensure-computations-occur-within-a-set-cycle-time .

    There are many different ways to implement inter-processor communication (IPC). As of SDK 8.3, the AM62x TI SDKs for AM62x support Linux A53 <-> PRU RPMsg, and Linux A53 <-> M4F (when M4F is used as a non-isolated, general purpose real-time core).

    Regards,

    Nick

  • +1 in reply to Nick Saulnier
    TI__Guru** 101170 points

    Following up on the naming convention for PSRAMECC_16K0_RAM:

    "16K is the depth.  Width is 32 bits so total size is 64K Bytes"