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TMDS64GPEVM: How to configure to use CPSW3g

Daisuke Maeda
Guru 20245 points
Part Number: TMDS64GPEVM
Other Parts Discussed in Thread: SYSCONFIG, DP83869

Our customer wants to use CPSW3g to test TSN on TMDS64GPEVM.

e2e.ti.com/.../am6442-linux-time-sensitive-networking-on-sitara-processors-including-am64x

On the TMDS64GPEVM, the CPSW and ICSSG RGMII signals are multiplexed internally, but the MDIO signals are multiplexed via the IO expander, which is controlled by GPIO.

Does the CPSW3g driver in Processor SDK Linux configure the hardware to use CPSW3g instead of ICSSG on the TMDS64GPEVM? In other words, does the driver control GPIO for the multiplexed MDIO?

software-dl.ti.com/.../CPSW3g.html

Best regards,

Daisuke

  • 0
    TI__Mastermind 40410 points

    Hi,

    I will need to ask a colleague who is the TSN expert. Currently the colleague is out of the office until next week. 

    Best Regards,

    Schuyler

  • 0 in reply to Schuyler Patton
    Guru 20245 points

    Hi Schuyler-san,

    Thank you for your reply.

    Our customer wants to use the CPSW_RGMII1 port and the CPSW_RGMII2 port, not the PRG1_RGMII1 port and the PRG1_RGMII2 port, on TMDS64GPEVM.

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

  • 0 in reply to Schuyler Patton
    Guru 20245 points

    Hi Schuyler-san,

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

  • 0 in reply to Schuyler Patton
    Guru 20245 points

    Hi Schuyler-san,

    Sorry for the repeated prompting.

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

  • 0 in reply to Schuyler Patton
    Guru 20245 points

    Hi Schuyler-san,

    Sorry for the repeated prompting.

    Daisuke Maeda said:
    Our customer wants to use the CPSW_RGMII1 port and the CPSW_RGMII2 port, not the PRG1_RGMII1 port and the PRG1_RGMII2 port, on TMDS64GPEVM.

    Could you tell me how to configure to use the two CPSW3g ports?

    Daisuke Maeda said:
    Does the CPSW3g driver in Processor SDK Linux configure the hardware to use CPSW3g instead of ICSSG on the TMDS64GPEVM? In other words, does the driver control GPIO for the multiplexed MDIO?

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 40410 points

    Hi Daisuke,

    The CPSW3G driver is strictly for the CPSW and will not support the ICCSG.  The CPSW and MDIO driver will read the Linux DTS file to set the pin mux for the appropriate interface CPSW or ICSSG. The AM64 SK-EVM DTS for example is setup for CPSW interface only on the package pins. 

    Best Regards,

    Schuyler

  • 0 in reply to Schuyler Patton
    Guru 20245 points

    Hi Schuyler-san,

    Thank you for your reply.

    Schuyler Patton said:
    The CPSW and MDIO driver will read the Linux DTS file to set the pin mux for the appropriate interface CPSW or ICSSG. The AM64 SK-EVM DTS for example is setup for CPSW interface only on the package pins.

    I understand that the CPSW3G driver does not support the multiplexed MDIO signals via the IO expander on the TMDS64GPEVM.

    Could you tell me how to setup the multiplexed MDIO signals via the IO expander for CPSW3G?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 40410 points

    Hi,

    The muxing is configured using the TI Sysconfig tool. The pin mux output from the Sysconfig tool is placed in the DTS file and compiled to a DTB file. If I understand your question the muxing is not with an external IO expander.

    Best Regards,

    Schuyler 

  • 0 in reply to Schuyler Patton
    Guru 20245 points

    Hi Schuyler-san,

    Thank you for your reply.

    Processor SDK Linux does not support to control the IO expander for the multiplexed MDIO signals on the TMDS64GPEVM?

    " The second PHY (connected to stacked RJ45 connector J21B) is interfaced to the PRG1_RGMII2 port of the SoC. This port is directly multiplexed with the CPSW_RGMII2 port. In order to select between CPSW and PRG operation, we need to multiplex the MDIO MDC signals from each controller to this PHY and the mux shall be controlled by a GPIO from IO expander. PRG1_RGMII2 is also internally multiplexed with PRG1_MII signals. The objective of the PHY used to connect this port is that the PHY should support both RGMII and MII modes, hence DP83869 (48 pin) PHY is selected."

    Best regards,

    Daisuke