Part Number: TMDS64GPEVM
On TMDS64GPEVM I have the Boot Mode configured for OSPI and the flash with SBL_NULL (Per "Flash SOC Initialization Binary" instructions.)
The UART console display the correct messages when boot:
Starting NULL Bootloader ...
DMSC Firmware Version 22.1.1--v2022.01 (Terrific Llam
DMSC Firmware revision 0x16
DMSC ABI revision 3.1
INFO: Bootloader_runCpu:151: CPU r5f1-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:151: CPU r5f1-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:151: CPU m4f0-0 is initialized to 400000000 Hz !!!
INFO: Bootloader_runCpu:151: CPU a530-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:151: CPU a530-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_loadSelfCpu:203: CPU r5f0-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_loadSelfCpu:203: CPU r5f0-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_runSelfCpu:213: All done, reseting self ...
In CCS (v11.2) I am getting stuck at OnTargetConnect() when try to connect to A53_0.
CortexA53_0: GEL Output: --->>> DDR4 Initialization is in progress ... <<<---
CortexA53_0: GEL Output: --->>> ECC Disabled <<<---
CortexA53_0: GEL Output: --->>> DDR controller programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR controller programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PI programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PI programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 0 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 0 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 1 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 1 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 0 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 2 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 1 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 1 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address slice 2 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 2 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> Set PHY registers for all FSPs simultaneously (multicast)... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY programming completed... <<<---
CortexA53_0: GEL Output: Debugging enabled
CortexA53_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_400MHz
CortexA53_0: GEL Output: hsdiv_value: 3
CortexA53_0: GEL Output: HSDIV reset asserted
CortexA53_0: GEL Output: HSDIV divider value programmed.
CortexA53_0: GEL Output: HSDIV reset de-asserted
CortexA53_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set.
CortexA53_0: GEL Output: Setting DDR4 frequency...
CortexA53_0: GEL Output: Triggering start bit from PI...
CortexA53_0: GEL Output: --->>> DDR PI initialization started... <<<---
CortexA53_0: GEL Output: Triggering start bit from CTL...
CortexA53_0: GEL Output: --->>> DDR CTL initialization started... <<<---
CortexA53_0: GEL Output: Polling PI DONE bit...
CortexA53_0: GEL Output: pi_int_status = 0x29C12001...
CortexA53_0: GEL Output: - PI_INIT_DONE_BIT set: The power-on initialization training in PI has been completed.
CortexA53_0: GEL Output: - PI_LVL_DONE_BIT set: The leveling operation has completed.
CortexA53_0: GEL Output: - PI_DLL_LOCK_STATE_CHANGE_BIT set: A state change has been detected on the dfi_init_complete signal after initialization.
CortexA53_0: GEL Output: - PI_RDLVL_GATE_DONE_BIT set: A read leveling gate training operation has been completed.
CortexA53_0: GEL Output: - PI_RDLVL_DONE_BIT set: A read leveling operation has been completed.
CortexA53_0: GEL Output: - PI_WRLVL_DONE_BIT set: A write leveling operation has been completed.
CortexA53_0: GEL Output: - PI_VREF_DONE_BIT set: A VREF setting operation has been completed.
CortexA53_0: GEL Output: - Not documented bit set.
CortexA53_0: GEL Output: ctl_int_status = 0x00000008...
If I boot in No Boot Mode and execute in CCS the script load_dmsc.js everything works fine:
Connecting to DMSC_Cortex_M3_0!
Fill R5F ATCM memory...
Writing While(1) for R5F
Loading DMSC Firmware ... /home/decameron/ti/mcu_plus_sdk_am64x_08_03_00_18/source/drivers/sciclient/soc/am64x_am243x/sysfw.bin
DMSC Firmware Load Done...
DMSC Firmware run starting now...
Connecting to MCU Cortex_R5_0!
Main Boot Mode is 120
Running the board configuration initialization from R5!
Happy Debugging!!
When try to connect to A53_0, OnTargetConnect() works fine:
CortexA53_0: GEL Output: --->>> DDR4 Initialization is in progress ... <<<---
CortexA53_0: GEL Output: --->>> ECC Disabled <<<---
CortexA53_0: GEL Output: --->>> DDR controller programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR controller programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PI programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PI programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 0 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 0 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 1 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 1 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 0 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 2 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 1 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 1 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address slice 2 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 2 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> Set PHY registers for all FSPs simultaneously (multicast)... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY programming completed... <<<---
CortexA53_0: GEL Output: Debugging enabled
CortexA53_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_400MHz
CortexA53_0: GEL Output: hsdiv_value: 3
CortexA53_0: GEL Output: HSDIV reset asserted
CortexA53_0: GEL Output: HSDIV divider value programmed.
CortexA53_0: GEL Output: HSDIV reset de-asserted
CortexA53_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set.
CortexA53_0: GEL Output: Setting DDR4 frequency...
CortexA53_0: GEL Output: Triggering start bit from PI...
CortexA53_0: GEL Output: --->>> DDR PI initialization started... <<<---
CortexA53_0: GEL Output: Triggering start bit from CTL...
CortexA53_0: GEL Output: --->>> DDR CTL initialization started... <<<---
CortexA53_0: GEL Output: Polling PI DONE bit...
CortexA53_0: GEL Output: pi_int_status = 0x29C02001...
CortexA53_0: GEL Output: - PI_INIT_DONE_BIT set: The power-on initialization training in PI has been completed.
CortexA53_0: GEL Output: - PI_LVL_DONE_BIT set: The leveling operation has completed.
CortexA53_0: GEL Output: - PI_RDLVL_GATE_DONE_BIT set: A read leveling gate training operation has been completed.
CortexA53_0: GEL Output: - PI_RDLVL_DONE_BIT set: A read leveling operation has been completed.
CortexA53_0: GEL Output: - PI_WRLVL_DONE_BIT set: A write leveling operation has been completed.
CortexA53_0: GEL Output: - PI_VREF_DONE_BIT set: A VREF setting operation has been completed.
CortexA53_0: GEL Output: - Not documented bit set.
CortexA53_0: GEL Output: ctl_int_status = 0x02000000...
CortexA53_0: GEL Output: --->>> DDR Initialization completed... <<<---
CortexA53_0: GEL Output: --->>> DDR4 Initialization is DONE! <<<---
I suspect this has to do with the initialization script for A53_0 in target configuration when boot with SBL NULL.
The documentation calls for changing the Initialization Script only for R5_0_0 (CPU_reset.gel) but A53_0 still has AM64x_GP_EVM.gel as Initialization Script.
Please advise
Thank you.
